80CL31 Datasheet, PDF (19/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
The signal to load S0BUF and RB8, and to set Rl, will be generated
if, and only if, the following conditions are met at the time the final
shift pulse is generated.
1. Rl = 0, and
2. Either SM2 = 0 or the received 9th data bit = 1
If either of these conditions is not met, the received frame is
irretrievably lost, and Rl is not set. If both conditions are met, the
received 9th data bit goes into RB8, and the first 8 data bits 90 into
S0BUF. One bit time later, whether the above conditions were met or
not, the unit goes back to looking for a 1-to-0 transition at the RxD
input.
1.6 Interrupt System
External events and the real-time-driven on-chip peripherals require
service by the CPU asynchronous to do execution of any particular
section of code. To tie the asynchronous activities of these functions
to normal program execution, a multiple-source, two-priority-level,
nested interrupt system is provided. The 80CL51 acknowledges
interrupt requests from thirteen sources as follows:
– INT0 and INT1
– Timer 0 and Timer 1
– UART serial I/O
– INT2 to INT9 (Port 1)
Each interrupt vectors to a separate location in program memory for
its service routine. Each source can be individually enabled or
disabled by corresponding bits in the Interrupt Enable Registers (IE,
IEO). The priority level is selected via the Interrupt Priority register
(IP0, IP1). All enabled sources can be globally disabled or enabled.
1.6.1 External Interrupts INT2/INT9
Port 1 lines serve an alternative purpose as eight additional
interrupts INT2 to INT9. When enabled, each of these lines may
“wake-up” the device from Power-down mode. Using the IX1
register, each pin may be initialized to either active HIGH or LOW.
IRQ1 is the interrupt request flag register. Each flag, if the interrupt
is enabled, will be set on an interrupt request but must be cleared by
software, i.e. via the interrupt software or when the interrupt is
disabled.
The Port 1 interrupts are level sensitive. A Port 1 interrupt will be
recognized when a level (HIGH or LOW depending on Interrupt
Polarity Register IX1) on P1x is held active for at least one machine
cycle. The Interrupt Request is not served until the next machine
cycle.
INTERRUPT
SOURCES
X0
S0
X5
T0
X6
X1
X2
X7
T1
X3
X8
X4
X9
IEN0/1
IP0/1
REGISTERS
PRIORITY
HIGH
LOW
GLOBAL ENABLE
Figure 11. Interrupt System
January 1995
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