80CL31 Datasheet, PDF (14/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
RECEIVE enables SHIFT CLOCK to the alternate output function
line of P3.1. SHIFT Clock makes transitions at S3P1 and S6P1 of
every machine cycle. at S6P2 of every machine cycle in which
RECEIVE is active, the contents of the receive shift register are
shifted to the left one position. The value that comes in from the right
is the value that was sampled at the P3.0 pin at S5P2 of the same
machine cycle.
As data bits come in from the right, 1s shift out to the left. When the
0 that was initially loaded into the right-most position arrives at the
left-most position in the shift register, it flags the RX Control block to
do one last shift and load S0BUF. At S1P1 of the 10th machine cycle
after the write to SCON that cleared Rl, RECEIVE is cleared as Rl is
set.
More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a
start bit (0), 8 data bits (LSB first), and a stop bit (1 ). On receive,
the stop bit goes into RB8 in SCON. In the 8051 the baud rate is
determined by the Timer 1 overflow rate.
Figure 8 shows a simplified functional diagram of the serial port in
Mode 1, and associated timings for transmit/receive.
Transmission is initiated by any instruction that uses S0BUF as a
destination register. The “write to S0BUF” signal also loads a 1 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter. (Thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to S0BUF” signal).
The transmission begins with activation of SEND which sends the
start bit to pin TxD. One bit time later, DATA is activated, enabling
the transmission of the output bit of the transmit shift register to TxD.
The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left.
When the MSB of the data byte is at the output position of the shift
register, then the 1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control unit to do one last shift
and then deactivate SEND and set Tl. This occurs at the 10th
divide-by-16 rollover after “write to S0BUF”. Reception is initiated by
a detected 1 -to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been
established. When a transition is detected, the divide-by-16 counter
is immediately reset, and 1FFH is written into the input shift register.
Resetting the divide-by-16 counter aligns its rollovers with the
boundaries of the incoming bit times. The 16 states of the counter
divide each bit time into 16th. At the 7th, 8th, and 9th counter states
of each bit time, the bit detector samples the value of RxD. The
value accepted is the value that was seen in at least 2 of the 3
samples. This is done for noise rejection. If the value accepted
during the first bit time is not 0, the receive circuits are reset and the
unit goes back to looking for another 1-to-0 transition. This is to
provide rejection of false start bits. If the start bit proves valid, it is
shifted into the input shift register, and reception of the rest of the
frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the
start bit arrives at the left-most position in the shift register, (which in
mode 1 is a 9-bit register), it flags the RX Control block to do one
last shift, loads S0BUF and RB8, and set Rl. The signal to load
S0BUF and RB8, and to set Rl, will generated if, and only if, the
following conditions are met at the time the final shift pulse is
generated.
1. R1 = 0, and
2. Either SM2 = 0, or the received stop bit = 1
If either of these two conditions is not met, the received frame is
irretrievably lost. If both conditions are met, the stop bit goes into
RB8, the 8 data bits go into S0BUF, and Rl is activated. At this time,
whether the above conditions are met or not, the unit goes back to
looking for a 1-to-0 transition in RxD.
More about modes 2 and 3
Eleven bits are transmitted (through TxD), or received (through
RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be
assigned the value of 0 or 1. On receive, the 9th data bit goes into
RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64
the oscillator frequency in Mode 2. Mode 3 may have a variable
baud rate generated from Timer 1.
Figures 9 and 10 show a functional diagram of the serial port in
Modes 2 and 3. The receive portion is exactly the same as in Mode
1. The transmit portion differs from Mode 1 only in the 9th bit of the
transmit shift register.
Transmission is initiated by any instruction that uses S0BUF as a
destination register. The “write to S0BUF” signal also loads TB8 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter (thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to S0BUF” signal). The
transmission begins with activation of SEND, which puts the start bit
at TxD. One bit time later, DATA is activated, which enables the
output bit of the transmit shift register to TxD. One bit time later,
DATA is activated, which enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs one bit time after that.
The first shift clocks a 1 (the stop bit) into the 9th bit position of the
shift register. Thereafter, only zeros are clocked in. Thus, as data
bits shift out to the right, zeros are clocked in from the left. Then TB8
is at the output position of the shift register, then the stop bit is just to
the left of TB8, and all positions to the left of that contains zeros.
This condition flags the TX Control unit to do one last shift and then
deactivate SEND and set Tl. This occurs at the 11th divide-by-16
rollover after “write to S0BUF”.
Reception is initiated by a detected 1-to-0 transition at RxD. For this
purpose RxD is sampled at a rate of 16 times whatever baud rate
has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFFH is written to
the input shift register.
At the 7th, 8th and 9th counter states of each bit time, the bit
detector samples the value of RxD. The value accepted is the value
that was seen in at least 2 of the 3 samples. If the value accepted
during the first bit time is not 0, the receive circuits are reset and the
unit goes back to looking for another 1-to-0 transition. If the start bit
proves valid, it is shifted into the input shift register, and reception of
the rest of the frame will proceed. As data bits come in from the
right, 1s shift out to the left. When the start bit arrives at the left-most
position in the shift register (which in Modes 2 and 3 is a 9-bit
register), it flags the RX Control block to do one last shift, load
S0BUF and RB8, and set Rl.
January 1995
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