80CL31 Datasheet, PDF (25/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
1.8 Reset Circuitry
To initialize the 80CL51, a reset is performed by either of two
methods:
– via the RST pin
– via a power-on-reset
It leaves the internal registers as follows:
REGISTER
ACC
B
DPL
DPH
IEN0
IEN1
IP0
IP1
IX1
IRQ1
PCH
PCL
PCON
PSW
P0-P3
S0BUF
S0CPN
SP
TCON
TH0, TH1
TL0, TH1
TL0, TL1
TMOD
CONTENT
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
XX00 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0XXX 0000
0000 0000
1111 1111
XXXX XXXX
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
The reset state of the port pins is mask- programmable and can
therefore be defined by the user.
The standard reset value for port P0-P3 is 1111 1111.
The reset input to the 80CL51 is RST pin 9. A Schmitt trigger
qualifies the input for noise rejection. The output of the Schmitt
trigger is sampled by the reset circuitry every machine cycle.
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (24 oscillator periods), while the oscillator is
running. The CPU responds by generating an internal reset. Port
pins adopt their reset state immediately after RST goes HIGH.
During reset ALE and PSEN are held HIGH.
The external reset is asynchronous to the internal clock. The RST
pin is sampled during State 5, Phase 2 of every machine cycle. After
a HIGH is detected at the RST pin, an internal reset is repeated
every cycle until RST goes LOW.
The internal RAM is not affected by reset. When V_DD is turned on
the RAM contents are indeterminate.
1.8.1 Power-on reset
The 80CL51 contains on-chip circuitry which switch the port pins to
the customer defined logic level as soon as V_DD exceeds
1.3V. As soon as the minimum supply voltage is reached, the
oscillator will start up. However, to ensure that the oscillator is stable
before the controller starts, the clock signals are gated away from
the CPU for a further 1536 oscillator periods. During that time the
CPU is held in a reset state.
A hysteresis of approximately 50 mV at a typical power-on switching
level of 1.3 V will ensure correct operation.
The on-chip Power-on circuitry can be switched off via the mask
option “OFF”. This option reduces the power-down current to
typically 800µA and can be chosen if external reset circuitry is used.
For applications not requiring the internal reset option, “OFF” should
be chosen.
An automatic reset can be obtained at power-on by connecting the
RST pin to V_DD via a 10µF capacitor. At power-on, the voltage on
the RST pin is equal to V_DD minus the capacitor voltage, and
decreases from V_DD as the capacitor discharges through the
internal resistor R_RST to ground. The larger the capacitor, the more
slowly V_RST decreases V_RST must remain above the lower threshold
of the Schmitt trigger long enough to effect a complete reset. The
time required is the oscillator start-up time, plus 2 machine cycles.
1.9 P80CL31: ROMless version of P80CL51
The P80CL31 is a low voltage ROMless version of the P80CL51
microcontroller. The mask options on the P80CL31 are fixed as
follows:
• Port options: all ports have option “1S”, i.e., standard port, high
after reset
• Oscillator option: OSC3
• Power-on Reset option: OFF
1.10 P80C51: 5V standard version
The P80C51 is a 5V version of the low voltage P80CL51
microcontroller. All functional features of the P80CL51 are
maintained in the P80C51 with the exception of the mask options.
The mask options on the P80C51 are as follows:
• Port options: all ports have option “1S”, i.e., standard port, high
after reset.
• Oscillator options: OSC3
• Power-on Reset option: OFF
January 1995
RST
SCHMITT
TRIGGER
RESET
CIRCUITRY
Figure 17. Reset Configuration at RST Pin
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