80CL31 Datasheet, PDF (29/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
5.0 AC CHARACTERISTICS
V_DD = 5 V; V_SS = 0V; T_amb = -40 to +85°C; C_L = 50 pF for Port 0, ALE and PSEN; C_L = 40pF for all other outputs, unless otherwise specified.
PROGRAM MEMORY (See Figure 20)
SYMBOL
PARAMETER
t_LL
ALE pulse duration
t_AL
Address set-up time to ALE
t_LA
Address hold time to ALE
t_LC
Time from ALE to control pulse PSEN
t_LIV
Time from ALE to valid instruction input
t_CC
Control pulse duration PSEN
t_CIV
Time from PSEN to valid instruction input
t_CI
Input instruction hold time after PSEN
t_CIF
Input instruction float delay after PSEN
t_AIV
Address to valid instruction input
t_AFC
Address float time to PSEN
MIN.
2T_CK-40
T_CK-40
T_CK-35
T_CK-25
-
3T_CK-35
-
0
-
-
0
TYP.
-
-
-
-
-
-
-
-
-
-
-
VARIABLE CLOCK
MAX.
UNIT
-
ns
-
ns
-
ns
-
ns
4T_CK-100
ns
-
ns
3T_CK-125
ns
-
ns
T_CK-20
ns
5T_CK-115
ns
-
ns
EXTERNAL DATA MEMORY (See Figures 21 and 22)
SYMBOL
PARAMETER
MIN.
TYP.
VARIABLE CLOCK
MAX.
UNIT
t_RR
t_WW
t_LA
t_RD
t_DFR
t_LD
t_AD
t_LW
t_AW
t_WHLH
t_DWX
t_DW
t_WD
t_WAFR
RD pulse duration
WR pulse duration
Address hold time after ALE
RD to valid data input
Data float delay after RD
Time from ALE to valid data input
Address to valid data input
Time from ALE to RD and WR
Time from address to RD and WR
Time from RD or WR HIGH to ALE HIGH
Data valid to WR transition
Data set-up time before WR
Data hold time after WR
Address float delay after RD (Note 1)
6T_CK-100
-
-
ns
6T_CK-100
-
-
ns
T_CK-35
-
-
ns
T_CK-35
-
5T_CK-165
ns
-
-
2T_CK-70
ns
-
-
8T_CK-150
ns
-
-
9T_CK-165
ns
3T_CK-50
-
3T_CK+50
ns
4T_CK-130
-
-
ns
T_CK-40
-
T_CK-40
ns
T_CK-60
-
-
ns
T_CK-150
-
-
ns
T_CK-50
-
-
ns
-
-
12
ns
NOTE:
1. Interfacing the 80CL51 or P80C51 to devices with float times up to 75ns is permitted. This limited bus connection will not cause damage to
Port 0 drivers.
January 1995
29