80CL31 Datasheet, PDF (11/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
1.4.2 Power-down mode
The instruction setting PCON.1 is the last executed prior to going
into the Power-down mode. In Power-down mode the oscillator is
stopped. The contents of the on-chip RAM and SFRs are preserved.
The port pins output the values held by their respective SFRs. ALE
and PSEN are held LOW.
In the Power-down mode V_DD may be reduced to minimize power
consumption. However, the supply voltage must not be reduced until
Power-down mode is active, and must be restored before the
hardware reset is applied and frees the oscillator. Reset must be
held active until the oscillator has restarted and stabilized.
The wake-up operation after power-down in this controller has two
basic approaches:
1.4.2.1 Wake-up using INT2 to INT9
If INT2 to INT9 are enabled, the 80CL51 can be awakened from
power-down mode with the external interrupts. To ensure that the
oscillator is stable before the controller restarts, the internal clock
will remain inactive for 1536 oscillator periods. This is controlled by
an on-chip delay counter.
1.4.2.2 Wake-up using RESET
To wake-up the 80CL51 the RESET pin has to be kept HIGH for a
minimum of 24 oscillator periods. The on-chip delay counter is
inactive. The user has to ensure that the oscillator is stable before
any operation is attempted. Figure 5 illustrates the two possibilities
for wake-up.
1.4.3 Idle mode
The instruction that sets PCON.0 is the last instruction executed
before going into Idle mode. Once in the Idle mode, the internal
clock is gated away from the CPU, but not from the Interrupt, Timer
and Serial port functions. The CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status Word and
Accumulator. The RAM and all other registers maintain their data
during Idle mode. The port pins retain the logical states they held at
Idle mode activation. ALE and PSEN hold at the logic HIGH level.
There are two methods used to terminate the Idle mode. Activation
of any enabled interrupt will cause PCON to be cleared by
hardware, terminating Idle mode. The interrupt is serviced, and
following the instruction RETI, the next instruction to be executed
will be the one following the instruction that put the device in the Idle
mode.
Flag bits GF0 and GF1 may be used to determine whether the
interrupt was received during normal execution or Idle mode. For
example, the instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by an interrupt,
the service routine can examine the status of the flag bits.
The second method of terminating the Idle mode is with an external
hardware reset. Since the oscillator is still running, the hardware
reset is required to be active for only two machine cycles to
complete the reset operation.
Reset redefines all SFRs, but does not affect the on-chip RAM.
The status of the external pins during Idle and Power-down mode is
shown in Table 1. If the Power-down mode is activated while
accessing external memory, port data held in the Special Function
Register P2 is restored to Port 2. If the data is a logic 1, the port pin
is held HIGH during the Power-down mode by the strong pull up
transistor p1 (see Figure 3(a)).
Table 1. Status of the External Pins During Idle and Power-down Mode
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
Idle
internal
1
1
Port Data
Port Data
Idle
external
1
1
Floating
Port Data
Power-down internal
0
0
Port Data
Port Data
Power-down external
0
0
Floating
Port Data
PORT 2
Port Data
Address
Port Data
Port Data
PORT 3
Port Data
Port Data
Port Data
Port Data
POWER-DOWN
RESET-PIN
EXTERNAL INTERRUPT
OSCILLATOR
DELAY COUNTER
1536 PERIODS
>24 PERIODS
Figure 5. Wake-up Operation
January 1995
11