80CL31 Datasheet, PDF (12/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
1.5 Standard serial interface SI0: UART
This serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received
byte has been read from the register. (However, if the first byte still
hasn’t been read by the time reception of the second byte is
complete, one of the bytes will be lost). The serial port receive and
transmit registers are both accessed at Special Function Register
S0BUF. Writing to S0BUF loads the transmit register, and reading
S0BUF loads the transmit register, and reading S0BUF accesses a
physically separate receive register.
The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/ received (LSB first). The
baud is fixed at 1/12 the oscillator frequency.
Mode 1:
10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Mode 2:
11 bits are transmitted (through TxD) or received (through
RxD): start bit (0), 8 data bits (LSB first), a programmable
9th data bit, and a stop bit (1). On Transmit, the 9th data
bit (TB8 in SCON) can be assigned the value of 0 or 1.
Or, for example, the parity bit (P, in the PSW) could be
moved into TB8. On receive, the 9th data bit goes into
RB8 in Special Function Register SCON, while the stop
bit is ignored. The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
Mode 3:
11 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except
baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that
uses S0BUF as a destination register. Reception is initiated in Mode
0 by the condition Rl = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
1.5.1 Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte, however,
will interrupt all slaves, so that each slave can examine the received
byte and see if it is being addressed. The addressed slave will clear
its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is
received.
1.5.2 Serial port control register
The serial port control and status register is the Special Function
Register S0CON, shown in Figure 6. The register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (T1 and
R1). See next page.
Baud Rates
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator
Frequency /12. The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register PCON. If SMOD = 0 (which is
the value on reset), the baud rate is 1/64 the oscillator frequency. If
SMOD = 1, the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = (2^SMOD/64)(Oscillator Frequency)
The baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate.
Using Timer 1 to generate baud rates
When Timer 1 is used as the baud rate generator, the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate and the
value of SMOD as follows:
(2^SMOD/32)(Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either “timer” or “counter”
operation, and in any of its 3 running modes. In the most typical
applications, it is configured for “timer operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is
given by the formula:
Mode 1, 3 Baud Rate =
{(2^SMOD/32) (Oscillator Frequency)} / {12 (256 - (TH 1 )}
One can achieve very low baud rates with Timer 1 by leaving the
Timer 1 interrupt enabled, and configuring this Timer to run as a
16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1
interrupt to do a 16-bit software reload. Table 2 lists various
commonly used baud rates and how they can be obtained from
Timer 1.
More about Mode 0
Figure 7 shows a simplified functional diagram of the serial port in
Mode 0, and associated timing. Transmission is initiated by any
instruction that uses S0BUF as a destination register. The “write to
S0BUF” signal at S6P2 also loads a 1 into the 9th position of the
transmit shift register and tells the TX Control block to commence a
transmission. The internal timing is such that the one full machine
cycle will elapse between “write to S0BUF”, and activation of SEND.
SEND enables the output of the shift register to the alternate output
function line of P3.0 and also enables SHIFT CLOCK to the
alternate output function line of P3.1. SHIFT CLOCK is low during
S3, S4, and S5 of every machine cycle, and high during S6, S1 and
S2. At S6P2 of every machine cycle in which SEND is active, the
contents of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that was initially loaded into the 9th position is just to the
left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions occur at
S1P1 of the 10th machine cycle after “write to S0BUF”.
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2
of the next machine cycle, the RX Control unit writes the bits
11111110 to the receive shift register, and in the next clock phase
activates RECEIVE.
January 1995
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