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PSMN4R0-60YS_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel LFPAK 60 V, 4.0 mΩ standard level FET
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NXP Semiconductors
PSMN4R0-60YS
N-channel LFPAK 60 V, 4.0 mΩ standard level FET
Symbol
Parameter
Conditions
Ciss
input capacitance
VDS = 30 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 30 V; RL = 0.4 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 30 V
120
gfs
(S)
80
003aad810
20
RDSon
(mΩ)
15
10
40
5
Min Typ Max Unit
-
3501 -
pF
-
457 -
pF
-
240 -
pF
-
23
-
ns
-
24
-
ns
-
44
-
ns
-
14
-
ns
-
0.8 1.2 V
-
43
-
ns
-
58
-
nC
003aad813
0
0
30
60
90
ID (A)
Fig. 5. Forward transconductance as a function of
drain current; typical values
0
0
5
10
15
20
VGS (V)
Fig. 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values
PSMN4R0-60YS
Product data sheet
All information provided in this document is subject to legal disclaimers.
14 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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