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| PSMN1R0-30YLC_15 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology | |||
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NXP Semiconductors
PSMN1R0-30YLC
N-channel 30 V 1.15 m⦠logic level MOSFET in LFPAK using
NextPower technology
Symbol
Parameter
Conditions
RG
gate resistance
f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 15 V; VGS = 10 V;
Fig. 14; Fig. 15
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 15; Fig. 14
ID = 0 A; VDS = 0 V; VGS = 10 V; Fig. 15
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 14; Fig. 15
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V; Fig. 14
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
td(off)
turn-off delay time
tf
fall time
Qoss
output charge
VGS = 0 V; VDS = 15 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 15 V
ta
reverse recovery rise IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
time
VDS = 15 V; Fig. 18
tb
reverse recovery fall
time
Min Typ Max Unit
-
1.1 2.2 Ω
-
103.5 145 nC
-
50
70
nC
-
96.5 -
nC
-
12.9 -
nC
-
10.1 -
nC
-
2.8 -
nC
-
14.6 26
nC
-
2.2 -
V
3322 6645 9968 pF
605 1210 1815 pF
240 481 842 pF
-
44
-
ns
-
77
-
ns
-
108 -
ns
-
60
-
ns
-
35.2 -
nC
-
0.8 1.1 V
-
45
-
ns
-
67
-
nC
-
28.5 -
ns
-
16.5 -
ns
PSMN1R0-30YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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