PSMN020-30MLC_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33 using TrenchMOS Technology

NXP Semiconductors
PSMN020-30MLC
N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33 using
TrenchMOS Technology
Symbol
Parameter
Conditions
C_iss
input capacitance
V_DS = 15 V; V_GS = 0 V; f = 1 MHz;
C_oss
output capacitance
T_j = 25 °C; Fig. 14
C_rss
reverse transfer
capacitance
t_d(on)
t_r
turn-on delay time
rise time
V_DS = 15 V; R_L = 3 Ω; V_GS = 4.5 V;
R_G(ext) = 5 Ω
t_d(off)
turn-off delay time
t_f
fall time
Q_oss
output charge
V_GS = 0 V; V_DS = 15 V; f = 1 MHz;
T_j = 25 °C
Source-drain diode
V_SD
source-drain voltage I_S = 5 A; V_GS = 0 V; T_j = 25 °C; Fig. 15
t_rr
reverse recovery time I_S = 5 A; dI_S/dt = -100 A/µs; V_GS = 0 V;
Q_r
recovered charge
V_DS = 15 V
t_a
reverse recovery rise V_GS = 0 V; I_S = 5 A; dI_S/dt = -100 A/µs;
time
V_DS = 15 V; Fig. 16
t_b
reverse recovery fall
time
Min Typ Max Unit
-
430 -
pF
-
120 -
pF
-
70
-
pF
-
6.1 -
ns
-
7.2 -
ns
-
10.1 -
ns
-
5.1 -
ns
-
2.3 -
nC
-
0.89 1.1 V
-
13.5 -
ns
-
5.1 -
nC
-
6.3 -
ns
-
7.2 -
ns
40
I_D
(A)
10 V
30
4.5 V
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3.5 V
50
R_DSon
40
003aak272
30
20
V_GS = 3 V
20
2.8 V
10
2.6 V
2.4 V
2.2 V
0
0
0.5
1
1.5
2
2.5
3
V_DS (V)
10
0
0 2 4 6 8 10 12 14 16
V_GS (V)
Fig. 6. Output characteristics; drain current as a
Fig. 7. Drain-source on-state resistance as a function
function of drain-source voltage; typical values
of gate-source voltage; typical values
PSMN020-30MLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
4 September 2012
© NXP B.V. 2012. All rights reserved
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