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SAA8116 Datasheet, PDF (51/60 Pages) NXP Semiconductors – Digital PC-camera signal processor including microcontroller and USB interface
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Philips Semiconductors
Digital PC-camera signal processor including
microcontroller and USB interface
Product specification
SAA8116
TIMING
VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C.
SYMBOL
PARAMETER
Data input related to ASCLK for CCD sensors; (see Fig.10)
CONDITIONS MIN. TYP. MAX. UNIT
PINS PXL0 TO PXL7
tsu(i)(D)
th(i)(D)
data input set-up time
data input hold time
1.5 −
−
ns
1.5 −
−
ns
PPG high-speed pulses for SONY ICX098AK VGA CCD sensor at 30 fps; (see Fig.11)
td1
delay between falling edge FH2 and rising edge FH1
td2
delay between rising edge FH2 and falling edge FH1
td3
delay between falling edge FH1 and rising edge FCDS
td4
delay between rising edge FH1 and rising edge FS
td5
delay between rising edge FH1 and falling edge RG
td6
delay between falling edge ASCLK and rising
edge FH1
−4
−2
0
ns
0
1.5 3
ns
10.5 12
13.5 ns
10
12.5 15
ns
0
2
4
ns
−3
−1.5 0
ns
td7
delay between rising edge ASCLK and falling
edge FH1
2
6
10
ns
tWH(FH1)
tWL(FH2)
tWL(FCDS)
tWL(FS)
tWL(RG)
tWL(ASCLK)
tr
FH1 pulse width HIGH
FH2 pulse width LOW
FCDS pulse width LOW
FS pulse width LOW
RG pulse width LOW
ASCLK pulse width LOW
rise time
pulse FH1
pulse FH2
note 1
38
39.5 −
ns
41
42.5 −
ns
6
7
−
ns
18
20.5 −
ns
20
21.5 −
ns
40
43.5 −
ns
−
4
−
ns
−
4
−
ns
pulse RG
−
4
−
ns
pulse FCDS
pulse FS
−
4
−
ns
−
4
−
ns
tf
fall time
pulse FH1
pulse FH2
note 1
−
4
−
ns
−
4
−
ns
pulse RG
−
4
−
ns
pulse FCDS
pulse FS
−
4
−
ns
−
4
−
ns
Note
1. CL = 11 pF; Tamb = 25 °C.
2001 May 04
51
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