SAA8116 Datasheet, PDF (18/60 Pages) NXP Semiconductors – Digital PC-camera signal processor including microcontroller and USB interface

Philips Semiconductors
Digital PC-camera signal processor including
microcontroller and USB interface
Product specification
SAA8116
Table 5 80C51 Special Function Registers (SFR)
SFR
NAME
DESCRIPTION
B
B register
ACC accumulator
SIADR serial interface address
SIDAT serial interface data
SISTA serial interface status
SICON serial interface control
PSW program status word
P4
Port 4
IP
interrupt priority
P3
Port 3
IE
interrupt enable
P2
Port 2
SBUF serial data buffer
SCON serial controller
P1
Port 1
TH1 timer high 1
TH0 timer high 0
TL1 timer low 1
TL0 timer low 0
TMOD timer mode
TCON timer control
PCON power control
DPH data pointer high
DPLl data pointer low
SP
stack pointer
P0
Port 0
SFR
ADDRESS ₇
6
F0H
B7
B6
E0H
ACC7 ACC6
DBH
SA6 SA5
DAH
SD7 SD6
D9H
ST7 ST6
D8H
CR2 ENS1
D0H
CY AC
C0H
P4.7 P4.6
B8H
−
IP6
B0H
RD WR
A8H
EA IE6
A0H (AD15) AD14
99H
−
−
98H
SM0 SM1
90H
SDA SCL
8DH
−
−
8CH
8BH
−
−
−
−
8AH
−
−
89H
GATE C/T
88H
TF1 TR1
87H
−
−
83H
−
−
82H
−
−
81H
SP7 SP6
80H
P0.7 P0.6
5
B5
ACC5
SA4
SD5
ST5
STA
F0
P4.5
IP5
T1
IE5
AD13
−
SM2
P1.5
−
−
−
−
M1
TF0
−
−
−
SP5
P0.5
DATA BIT
4
3
B4
ACC4
SA3
SD4
ST4
STO
RS1
P4.4
IP4
T0
IE4
AD12
−
REN
P1.4
−
−
−
−
M0
TR0
−
−
−
SP4
P0.4
B3
ACC3
SA2
SD3
ST3
SI
RS0
P4.3
PT1
INT1
ET1
AD11
−
TB8
P1.3
−
−
−
−
GATE
IE1
−
−
−
SP3
P0.3
2
B2
ACC2
SA1
SD2
0
AA
OV
P4.2
PX1
INT0
EX1
AD10
−
RB8
P1.2
−
−
−
−
C/T
IT1
−
−
−
SP2
P0.2
1
B1
ACC1
SA0
SD1
0
CR1
−
P4.1
PT0
TXD
ET0
AD9
−
T1
P1.1
−
−
−
−
M1
IE0
PD
−
−
SP1
P0.1
0
B0
ACC0
GC
SD0
0
CR0
P
P4.0
PX0
RXD
EX0
AD8
−
R1
P1.0
−
−
−
−
M0
IT0
IDL
−
−
SP0
P0.0
Audio
The SAA8116 contains a microphone supply, including a
low-drop electronic supply filter, and an amplifier circuit
composed of two stages: a Low Noise Amplifier (LNA) and
a variable gain amplifier (VGA). The LNA has a fixed gain
of 30 dB while the VGA can be programmed between
0 and 30 dB in steps of 2 dB. The frequency transfer
characteristic of the audio path must be controlled via
external high-pass or low-pass filters.
The PLL converts the 48 MHz to 256f_s (f_s = audio sample
frequency). There are three modes for the PLL to achieve
the sample frequencies of 48, 44.1 and 32 kHz or their
derivatives (see Table 6).
The bitstream ADC samples the mono audio signal. It runs
at an oversample rate of 256 times the base sample rate.
A decimator filter transforms the bitstream output to 16-bit
samples.
A digital mute option is available.
2001 May 04
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