SAA8116 Datasheet, PDF (44/60 Pages) NXP Semiconductors – Digital PC-camera signal processor including microcontroller and USB interface

Philips Semiconductors
Digital PC-camera signal processor including
microcontroller and USB interface
Product specification
SAA8116
Table 50 Register SET_ADDRESS (address: 0xD0H)
Detailed description of the write (1 byte) following command 0xD0H
BIT
76543210
PARAMETER
X
ENABLE_ADD: enable the function (by default = 0)
X X X X X X X DEVICE_address: set the USB assigned address (by default = 0)
Table 51 Register SET_EP_ENABLE (address: 0xD8H)
Detailed description of the write (1 byte) following command 0xD8H
BIT
76543210
PARAMETER
XXXXXXX
reserved
ENABLE_EP: enable end-point
0 Non-control end-points are disabled (by default)
10 Non-control end-points are enabled
Table 52 Register GETSET_MODE (address: 0xF3H)
Detailed description of the write (one byte) following command 0xF3H; notes 1, 2 and 3
BIT
76543210
PARAMETER
XXXXX
reserved
FIFO_ACTIVE: set the video FIFO status
0
FIFO is inactive; only zero-length packet are sent upstream
1
functional mode (by default)
ALWAYS_PLLCLOCK: control internal clock signals
0
clocks and PLL are stopped whenever not needed (e.g. suspend mode)
1
clocks and PLL are always running even in suspend mode (by default)
INTERRUPT_ONNAK: control transaction reporting
0 only successful transactions are reported
1 NAK is reported and generates an interrupt (by default)
Notes
1. GETSET_MODE command can write from 1 to 4 consecutive bytes. The detailed description above concerns byte 0.
2. GETSET_MODE bytes 1 and 2 are used to set the size of the isochronous video packets. Byte 1 corresponds to the
LSB to define the packet size. Bits 0 and 1 of byte 2 set the 2 MSBs. By default, the two bytes are forced to 0.
3. GETSET_MODE byte 3 sets the FIFO offset.
2001 May 04
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