TDA8757 Datasheet, PDF (28/37 Pages) NXP Semiconductors – Triple 8-bit ADC 170 Msps

Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Table 18: Examples of PLL settings and performance
V_CCA = V_DDD = V_CCD = V_CCO = 5 V; T_amb = 25 °C.
Video standards
f_ref
f_clk
N
(kHz) (MHz)
K_O
C_Z C_P
(MHz/V) (nF) (nF)
VGA: 640 × 480
VESA: 800 × 600
(SVGA 72 Hz)
VESA: 1024 × 768
(XGA 75 Hz)
VESA: 1280 × 1024
(SXGA 60 Hz)
VESA: 1280 × 1024
(SXGA 75 Hz)
VESA: 1600 × 1200
(UXGA 60 Hz)
31.469 25.175 800 20
48.08 50
1040 40
60.02 78.75 1312 40
63.98 108 1688 70
80.00 135 1688 70
75.00 162 2160 70
68 0.15
68 0.15
68 0.15
68 0.15
68 0.15
68 0.15
I_P Z Long-term time jitter ^[1]
(µA) (kΩ) _RMS-value
peak-to-peak
(ps)
value (ps)
200 4.5 242
1 452
700 1.6 225
1 350
400 4.5 120
720
400 3.2 98
588
400 4.5 70
420
400 4.5 65
390
[1] PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.
CKDATA
tCPH
n
DATA
In_−1
In
Vin
td(s)
Sample n
Sample n+1
Fig 10. Data timing; Dmx = 0; n = even pixel.
tCPL
tsu(d)(o)
In₊₁
th(o)
Sample n+2
50%
2.4 V
0.4 V
Sample n+3
FCE700
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-2
n-1
n
n+1
n+2
n+3
n+4
n+5
FCE701
Fig 11. Timing diagram; single port mode; Dmx = 0, Ckdd = 0, Ckdp = 0; n = even pixel.
9397 750 09457
Preliminary data
Rev. 07 — 28 February 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
28 of 37