TDA8757 Datasheet, PDF (11/37 Pages) NXP Semiconductors – Triple 8-bit ADC 170 Msps

Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Table 3: Pin description…continued
Symbol
Pin
Description
V_CCO(PLL)
126
n.c.
127
PLL output supply voltage
not connected
DGND1
128
digital ground 1
OE
129
output enable; active LOW (when OE is HIGH, the outputs are
high-impedance)
PD
130
power-down control input (IC is in Power-down mode when
this pin is HIGH)
CLP
131
clamp pulse input (clamp active HIGH)
HSYNC
132
horizontal synchronization pulse input
INV
133
PLL clock output inverter control input (invert when HIGH)
CKEXT
134
external clock input
COAST
135
PLL coast control input
CKREF
136
PLL reference clock input
V_CCD1
n.c.
137
digital supply voltage 1
138
not connected
AGND_PLL
139
CP
140
PLL analog ground
PLL filter input
CZ
141
PLL filter input
AGND_PLL
142
V_CCA(PLL)
143
n.c.
144
PLL analog ground
PLL analog supply voltage
not connected
GND_DP
exposed die pad connection
8. Functional description
This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals, coming
from an analog source, into digital data used by a LCD driver (pixel clock up to
170 MHz).
8.1 Analog video inputs
The RGB/YUV video inputs are externally AC coupled and are internally
DC polarized.
The synchronization signals are also used for the internal PLL and the gain
calibration.
If the green video signal has composite sync (sync on green), it is possible to extract
this composite sync by connecting the green signal to pin IN_SOG (AC coupled). When
the sync pulse amplitude is below 300 mV, the I²C-bus bit ‘Slevel’ has to be set to
logic 1 (see Figure 5). The maximum amplitude for the sync pulse is 600 mV.
The composite sync is available at pin SOG_O (TTL level compatible signal).
9397 750 09457
Preliminary data
Rev. 07 — 28 February 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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