TDA8757 Datasheet, PDF (12/37 Pages) NXP Semiconductors – Triple 8-bit ADC 170 Msps

Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
300 mV
to
600 mV
blank level
150 mV comparison level
set by I²C-bus bit Slevel = 0
150 mV
to
300 mV
blank level
80 mV comparison level
set by I²C-bus bit Slevel = 1
005aaa009
Fig 5. Sync level diagram.
If this function is not used, pin IN_SOG should be connected to the analog power
supply. In this event, pin SOG_O is at LOW-level TTL.
8.2 Clamps
Three independent parallel clamping circuits are used to clamp the video input
signals on several black levels. The clamping levels may be set from
−63.5 to +64 LSBs (RGB) and from +120 to +136 LSBs in steps of ¹â„₂ LSB (YUV).
They are controlled by changing the values in three 8-bit registers: OFFSETR,
OFFSETG and OFFSETB (see Table 5). Each clamp must be able to correct an
offset from ±100 mV to ±10 mV within 300 ns, and correct the total offset in 10 lines.
The clamping is done using the following principle: On the incoming of a TTL positive
going pulse supplied on pin CLP, three external capacitors are loaded independently
by the device in order to change the voltage level of each analog RGB input. The
capacitors are connected to pins CLP_R, CLP_G and CLP_B.
video signal
clamp
programming
CLP
Fig 6. Clamp definition.
9397 750 09457
Preliminary data
Clamp
= +128
Clamp
= +64
Clamp
=0
Clamp
= −63.5
Rev. 07 — 28 February 2002
255
constant level
ADC
0
constant level
FCE698
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
12 of 37