TDA8757 Datasheet, PDF (13/37 Pages) NXP Semiconductors – Triple 8-bit ADC 170 Msps

Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
8.2.1 Variable gain amplifiers
Three independent variable gain amplifiers are used to provide a full-scale input
signal to the 8-bit ADC for each channel. The gain adjustment range is designed so
that for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds
to the ADC full-scale input of 1 V (p-p).
To ensure that the gain does not vary over the whole operating temperature range, a
reference voltage V_ref = 2.5 V (DC) with a maximum variation of 100 ppm/°C, is
supplied externally on pin VREF.
The calibration of the gains is done using the following principle: On the incoming of a
pulse supplied to pin HSYNC, an internal multiplexer switches from the RGB video
signals to a reference voltage (¹â„₁₆V_ref). The ADCs inputs become this reference
signal and the three corresponding outputs are compared to pre-set values loaded in
three 7-bit registers: COARSER, COARSEG and COARSEB. Depending on the
result of the comparisons, the three gains are adjusted such that the ADC outputs
become equal to the pre-set values in the registers. The three gains are simply
controlled by changing the values in the COARSE registers.
The signal supplied on pin HSYNC, may be selected active HIGH or active LOW. The
choice is done through the serial interface by setting bit ‘Hlevel’ in the control register
(active HIGH when bit Hlevel = 0).
This active part of the signal has to occur during the blanking period of the signal in
order not to interrupt the active video. Normally the horizontal synchronization signal,
provided by the video source, is connected to pin HSYNC.
The values loaded in the gain registers (COARSER, COARSEG, COARSEB) are
chosen among 68 values (see Table 6).
A fine correction is also used to finely tune the gain on the three channels and to
compensate the channel-to-channel gain mismatch. The fine correction is done using
the following principle: the three binary codes, stored in the three 5-bit registers
(FINER, FINEG and FINEB) are converted into three analog voltages (with three
DACs) and are independently added to the reference voltage (¹â„₁₆V_ref). Thus, three
different reference voltages are used for the gain calibration of the three channels.
When the COARSE registers are set at full-scale, the resolution of the fine registers
corresponds to ¹â„₂ LSB peak-to-peak (see Equation 3).
8.2.2 Important recommendations
The clamping and the gain calibration requires two external signals (pulses). One
signal is connected to pin CLP and the other is connected to pin HSYNC. It is very
important that:
• The active part of these two signals occur during the blanking of the video signal,
in order not to interrupt or disturb the active video.
• The active part of these two signals does not overlap on each other, in order to
perform correctly the gain calibration and the clamping. Normally the clamp pulse
is sent after the end of the horizontal synchronization pulse.
9397 750 09457
Preliminary data
Rev. 07 — 28 February 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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