TDA8757 Datasheet, PDF (16/37 Pages) NXP Semiconductors – Triple 8-bit ADC 170 Msps

Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
It is possible to control the phase of the ADC clock (CKADC) through the serial
interface with the included digital phase-shift controller. The phase register (5 bits)
enables the phase to shift by steps of 11.25 °.
The CKREF signal is re-synchronized by the synchro-block on the CKADC clock. The
new reference is available on pin CKREFO. This synchronization may be done with
the CKREF signal directly, or with the output of the divider in the PLL (see Figure 3).
The selection is done via the serial interface by setting bit ‘Ckrs’ in the phase register
(Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO
is controlled through the serial interface by setting bit ‘Ckrp’ in register DEMUX
(positive polarity if Ckrp = 0). The width of this signal is fixed to 8 clock cycles.
The PLL also provides a CKDATA clock. This clock is synchronized on the data
outputs whatever the output mode.
It is possible to delay the CKDATA clock with a constant time (τ = 3 ns, compared to
the outputs) by setting bit ‘Ckdd’ to logic 1 in register DEMUX. It is also possible to
reverse the CKDATA clock, referenced to the outputs, by setting bit ‘Ckdp’ in
register DEMUX.
The maximum capacitive load for each clock output is 10 pF, and pin OE switches the
output status between active and high impedance (OE = HIGH).
If an external clock is used, it has to be connected to pin CKEXT. Bit ‘Ckext’ and
bit ‘Ckrs’ in the phase register have to be set at logic 1, and it is also important to
disconnect the internal PLL by using the following settings:
• Set bit ‘Do’ in the control register to logic 1.
• Set bits ‘Vco1’ and ‘Vco0’ in register VCO to logic 0.
CKREF
CKADC
CKREFO
Ckrp = 0
CKREFO
Ckrp = 1
Fig 8. Timing diagram; CKREFO; Dmx = 0.
8 clock periods
tCKAO
tCKREFO
FCE699
9397 750 09457
Preliminary data
There is a delay between the input signal on pin CKREF and the corresponding
output on pin CKREFO; see Figure 8. This delay is t_CKREFO:
t_CKREFO = either t_CKAO (if clock phase >01000) or t_CKAO + T_CLK(pixel) (if phase <01000)
t_CKAO = t_CLK(buffer) + t_{phase selector}
t_CLK(buffer)
=
tbf
and
t_phase
selector
=


-^p---^h-₂---^a_π---^s---^e-_
⋅
T _{CLK ( pixel)}
Rev. 07 — 28 February 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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