TDA8757 Datasheet, PDF (17/37 Pages) NXP Semiconductors – Triple 8-bit ADC 170 Msps

Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
9. I²C-bus and 3W-bus interfaces
9.1 Register definitions
The configuration of the registers is given in Table 4.
Table 4: I²C-bus and 3W-bus registers
Function Subaddress
Bit definition
name
A7 A6 A5 A4 A3 A2 A1 A0 MSB
SUBADDR
X
X
X
Mode
OFFSETR X X X X 0 0 0 0 Or7 Or6 Or5 Or4
COARSER X X X X 0 0 0 1 Or8 Cr6 Cr5 Cr4
FINER
XXXX0 0 1 0 X
X
X
Fr4
OFFSETG X X X X 0 0 1 1 Og7 Og6 Og5 Og4
COARSEG X X X X 0 1 0 0 Og8 Cg6 Cg5 Cg4
FINEG
XXXX0 1 0 1 X
X
Slevel Fg4
OFFSETB X X X X 0 1 1 0 Ob7 Ob6 Ob5 Ob4
COARSEB X X X X 0 1 1 1 Ob8 Cb6 Cb5 Cb4
FINEB
XXXX1 0 0 0 X
X
X
Fb4
CONTROL X X X X 1 0 0 1 Vlevel Hlevel Edge Up
VCO
X X X X 1 0 1 0 Z2 Z1 Z0 Vco1
DIVIDER X X X X 1 0 1 1 Di8 Di7 Di6 Di5
(LSB)
PHASE X X X X 1 1 0 0 Di0 Ckrs Ckext P4
DEMUX X X X X 1 1 0 1 Blk Cken Ckrp Ckdp
Sa3
Or3
Cr3
Fr3
Og3
Cg3
Fg3
Ob3
Cb3
Fb3
Do
Vco0
Di4
P3
Ckdd
Sa2
Or2
Cr2
Fr2
Og2
Cg2
Fg2
Ob2
Cb2
Fb2
Ip2
Di11
Di3
P2
Shift
LSB
Sa1 Sa0
Or1 Or0
Cr1 Cr0
Fr1 Fr0
Og1 Og0
Cg1 Cg0
Fg1 Fg0
Ob1 Ob0
Cb1 Cb0
Fb1 Fb0
Ip1 Ip0
Di10 Di9
Di2 Di1
P1 P0
Odda Dmx
Default
value
XXX1 0000
0111 1111
0010 0000
XXX0 0000
0111 1111
0010 0000
XXX0 0000
0111 1111
0010 0000
XXX0 0000
0000 0111
1011 1011
0100 1100
0000 0000
1000 0111
9.1.1 Subaddress
All the registers are defined by a subaddress of 7 bits: bit Mode refers to the mode
which is used with the I²C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of
each register.
Bit Mode, used only with the I²C-bus, allows two modes for the programming:
Mode 0
Mode 1
Each register is programmed independently, by giving its subaddress
and its content.
All the registers are programmed one after the other, by giving this initial
condition (XXX1 1111) as the subaddress state; thus, the registers are
changed following the predefined sequence of 16 bytes (from
subaddress 0000 to 1101).
The default values correspond to a VESA 1280 × 1024 at 75 Hz graphic mode.
9.1.2 Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in Table 5.
9397 750 09457
Preliminary data
Rev. 07 — 28 February 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
17 of 37