PMCM6501VPE_15 Datasheet, PDF (10/15 Pages) NXP Semiconductors – 12 V, P-channel Trench MOSFET

NXP Semiconductors
12. Package outline
WLCSP6: wafer level chip-size package; 6 bumps (3 x 2)
PMCM6501VPE
12 V, P-channel Trench MOSFET
PMCM6501VPE
D
AB
ball A1
index area
A₂
E
A
A₁
detail X
ball A1
index area
1
e₂
2
A
B
C
e
b
e₁
v CAB
wC
y₁ C
C
y
X
Dimensions (mm are the original dimensions)
0
1 mm
scale
Unit
A A₁ A₂
b
D
E
e e₁ e₂ v
w
y
max 0.375 0.215 0.160 0.275 1.51 1.01
mm nom 0.345 0.200 0.145 0.260 1.48 0.98 0.50 1.00 0.50 0.15 0.05 0.05
min 0.315 0.185 0.130 0.245 1.45 0.95
Note
Device back is metal coated on Drain potential.
Outline
version
References
IEC
JEDEC
JEITA
PMCM6501VPE
Fig. 19. Package outline WLCSP6 (OL-PMCM6501VPE)
PMCM6501VPE
Product data sheet
All information provided in this document is subject to legal disclaimers.
10 August 2015
European
projection
pmcm6501vpe-ssmos_po
Issue date
15-07-16
© NXP Semiconductors N.V. 2015. All rights reserved
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