MN101EFC3 Datasheet, PDF (8/46 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
- Watchdog timer
- Overrun detection cycle is selectable from fs/2¹⁶, fs/2¹⁸, fs/2²⁰
- Forced to reset inside LSI by hardware when a software processing error is detected twice
- Watchdog timer2
- Overrun detection cycle is selectable from frcs/2⁴, frcs/2⁵, frcs/2⁶, frcs/2⁷, frcs/2⁸, frcs/2⁹,
frcs/2¹⁰, frcs/2¹¹, frcs/2¹², frcs/2¹³, frcs/2¹⁴, frcs/2¹⁵
- Forced to reset inside LSI by hardware when a software processing error is detected twice
- Synchronous output function (Timer synchronous output, interrupt synchronous output)
- Latch data is output from port 8 at the event timing of synchronous output signal of timer 1,
timer 2, timer 7, or external interrupt2 (IRQ2)
- A/D converter 10 bit x 12 channels
- Data automatic transfer 1 system
ATC1
Data is automatically transferred in all memory space
- External interrupt activation/internal event activation/software activation
- Max. 255 byte continuous transfer
- Serial continuous transmission and reception is supported
- Burst transfer function (Including interrupt emergency stop)
- CAN Controller
- Channels: 1 channel
- CAN 2.0B specification basis
- Communication method: NRZ (Non-Return to Zero)
- Transmission line: Bidirectional 2-wire serial communication
- Communication speed: Max. 1 Mbps
- Data length: 0 to 8 byte
- Message frame: Standard frame and extended frame are supported
Standard frame format ID: 11 bits
Extended frame format ID: 29 bits
- Buffer size: 32 messages (32 x 132 bit)
- Interrupt 1 set
- Interrupt source
Transition from bus off state to error active state, or back transition
Publication date: November 2015