MN101EFC3 Datasheet, PDF (15/46 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
1.3.3 Pin Functions
Pins
VSS
VDD50
VDD18
OSC1
OSC2
XI
XO
NRST
ATRST
P00
P01
P02
P03
P04
P05
P20
P21
P22
P23
P24
P25
P26
P27
Table:1.3.2 Pin Functions
Pin No. I/O
10, 18 -
13
15
-
Other Functions
11
Input P25
12
Output P26
Functions
Descriptions
Power supply pins
Supply 1.8 V to 5.5 V to VDD50, and 0 V to VSS.
Connect 0.1 F and more than 1 F of bypass capacitor
for internal power stabilization.
Internal power output pin Outputs internal power voltage 1.8 V. Connect 0.1 F and
1 F of bypass capacitor between VDD18 and VSS pins
for internal power stabilization. This is the power pin for
microcontroller internal power supply. Do not connect
external power supply from this pin.
High-speed operation
clock input pin
High-speed operation
clock output pin
Connect these oscillation pins to ceramic oscillator or
crystal oscillator for high-speed operation clock.
For external clock input, input to OSC1 and open OSC2.
The chip will not operate with an external clock when
using either STOP mode or SLOW mode.
8
Input P90
9
Output P91
Low-speed operation
clock input pin
Low-speed operation
clock output pin
Connect these oscillation pins to ceramic oscillator or
crystal oscillator for low-speed operation clock.
For external clock input, input to XI and open XO. The
chip will not operate with an external clock when using
STOP mode.
7
Input P27
Reset pin
[Active low]
This pin resets the chip at power on, is allocated as P27
and contains an internal pull-up resistor (Type. 50 k.
Setting this pin low initializes the internal state of the LSI.
Thereafter, setting the input to high releases the reset.
The hardware waits for the system clock to stabilize, then
processes the reset interrupt.
Also, if “0” is written to P27 and the reset is initiated by
software, a low level will be output. The output has an
Nch open-drain configuration. If a capacitor is to be
inserted between NRST and VSS, it is recommended that
a discharge diode be placed between NRST and V_DD50.
6
Input
Auto reset setting pin
Input “H” to enable auto reset function and “L” to disable
this function
19
I/O LED0 OCD_DAT I/O port 0
A
20
LED1 TM9IOB
OCD_CL
K
21
LED2 TM7IOB
SBI0A RXD0A
22
LED3 TM8IOB
SBO0A TXD0A
6-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or out-
put by the P0DIR register.
A pull-up /pull-down resistor for each bit can be selected
individually by the P0PLUD register.
A pull-up/down resistor connection for each port can be
selected individually by the SELUD register. (However,
pull-up and pull-down resistors cannot be mixed.) At
reset, the input mode is selected and pull-up resistors are
disabled (high impedance).
23
LED4 TM0IOB
TM2IOB SBT0A
24
LED5
25
I/O IRQ0
26
IRQ1
27
IRQ2
28
IRQ3
29
IRQ4
11
OSC1
12
OSC2
I/O port 2
7-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or out-
put by the P2DIR register.
A pull-up resistor for each bit can be selected individually
by the P2PLU register.
At reset, the input mode is selected and pull-up resistors
are disabled (high impedance)
7
Input NRST
Input port 2
P27 is an Nch open-drain port. When “0” is written and
the reset is initiated by software, a low level will be output.
Publication date: November 2015