MN101EFC3 Datasheet, PDF (3/46 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
1.2 Hardware Functions
 Feature
- ROM capacity:76 KB to 128 KB
- RAM capacity: 6 KB to 10 KB
- Package: TQFP064-P-1010D (10 mm  10 mm / 0.5 mm pitch/ Halogen free *)
LQFP064-P-1414 (14 mm  14 mm / 0.8 mm pitch)
* Panasonic’s “halogen free” semiconductor products refer to the products made of molding resin and
interposer which conform to the following standards.
- Bromine: 900 ppm (Maximum Concentration Value)
- Chlorine: 900 ppm (Maximum Concentration Value)
- Bromine + Chlorine: 1500 ppm (Maximum Concentration Value)
The above-mentioned standards are based on the numerical value described in IEC61249-2-21.
Antimony and its compounds are not added intentionally.
- Machine Cycle:
High-speed mode
0.05 s/20 MHz (2.7 V to 5.5 V)
0.125 s/8 MHz (1.8 V to 5.5 V)
Low-speed mode
62.5 s/32 kHz (1.8 V to 5.5 V)
- Clock Gear Circuit:
Internal system clock speed is changeable by selecting division ratio of oscillation clock.
(Divided by 1, 2, 4, 16, 32, 64, 128)
- Oscillation Circuit: 4 types
High-speed (Internal oscillation: frc), High-speed (crystal/ceramic: fosc),
Low-speed (Internal oscillation: frcs), Low-speed (crystal/ceramic: fx)
High-speed internal oscillation 20 MHz / 16 MHz (selectable)
Low-speed internal oscillation 30 kHz
- Clock Multiplication Circuit:
PLL circuit output clock (fpll) fosc multiplied by 2, 3, 4, 5, 6, 8, 10,
1/2xfrc multiplied by 4, 5 enabled
* When clock multiplication circuit is not used, fpll = fosc or fpll = frc
* Selectable from high-speed clock for peripheral functions (fpll-div) fpll, fpll divided by 2, 4, 8, 16
Publication date: November 2015