MN101C115 Datasheet, PDF (59/170 Pages) Panasonic Semiconductor – Request for your special attention and precautions in using the technical information and semiconductors described in this book

Chapter 3 Port Functions
3-2-2 I/O Port Control Registers
This section describes the special function registers that control the
MN101C117's I/O ports.
s Data Registers
• PnOUT registers
Data registers to output to the ports.
Data written to these registers is output from the ports.
0
Low (Vss level) is output.
1
High (Vdd level) is output.
• PnIN registers
Data registers to input data from the ports.
The value of data at the pins can be input by reading these registers.
These are read-only registers.
0
Pin is low.
1
Pin is high.
Input and output registers are mapped to separate addresses.
To use these ports for I/O, configure them as I/O ports in the PnOMD/PnIMD registers,
described in this section.
s Direction Control Registers
• PnDIR registers
0
Input mode
1
Output mode
These registers set the port for use as an input or output.
s Pull-up/Pull-down Resistor Control Registers
• PnPLU registers
These register settings determine whether internal pull-up resistors are added to the ports.
0
No pull-up / pull-down resistor
1
Pull-up / Pull down resistor
• PnPLUD registers
These register settings determine whether internal pull-up or pull-down resistors are
added to the ports.
0
No pull-up / pull-down resistor
1
Pull-up / Pull down resistor
Port Control Registers ⁴⁵