MN101C115 Datasheet, PDF (48/170 Pages) Panasonic Semiconductor – Request for your special attention and precautions in using the technical information and semiconductors described in this book

Chapter 2 Basic CPU Functions
2-4-3 Interrupt Control Registers
Be sure to use the MIE flag of
the PSW register to write to all
interrupt control registers.
Interrupt control registers consist of the following: a non-maskable interrupt control
register (NMICR), external interrupt control registers (IRQnICR), and internal
interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR).
s Non-maskable Interrupt Control Register (NMICR)
Non-maskable interrupt factors are stored in the non-maskable interrupt control
register (NMICR), and are used when a non-maskable interrupt is generated.
NMICR
7
6
5
4
3
2
1
0
WDIR
(at reset: ------0-)
WDIR
Watchdog interrupt request flag
0
No interrupt request
1
Happens interrupt request
Figure 2-4-2 Non-maskable Interrupt Control Register (NMICR: X'03FE1', R/W)
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector will be disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.
s External Interrupt Control Registers (IRQnICR)
The external interrupt control registers (IRQnICR) control the interrupt level, valid
edge, and request/enable.
7
6
5
4
3
2
1
0
IRQnICR xxxLV1 xxxLV0 REDGn — — — xxxIE xxx R
(at reset: 000---00)
xxxIR
0
1
External interrupt request flag
No interrupt request
Happens interrupt request
xxxIE
0
1
External interrupt enable flag
Disable interrupt
Enable interrupt
REDGn^∗
0
1
External interrupt valid edge flag
Falling edge
Rising edge
xxxLV1 xxxLV0 Interrupt level flag for external interrupt
The CPU has interrupt levels from 0 to 3.
This flag sets the interrupt level for interrupt requests.
∗ n=0,1,2,3,4
Figure 2-4-3 External Interrupt Control Register
(IRQnICR: X'03FE2' to X'03FE3', X'03FEB' to X'03FED', R/W)
34 Interrupts