MN101C115 Datasheet, PDF (49/170 Pages) Panasonic Semiconductor – Request for your special attention and precautions in using the technical information and semiconductors described in this book

Chapter 2 Basic CPU Functions
s Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR)
The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR,
ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial
interrupts, A/D conversion complete interrupts, and interrupt request/enable.
Be sure to disable all interrupts before writing to these registors.
7
6
5
4
3
2
1
0
MnICR, TBICR, SCnICR, _{xxxLV1 xxxLV0 –}
–
–
– xxxIE xxxIR
ATCICR, ADICR
(at reset: 00----00)
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector will be disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.
xxxIR
0
1
Interrupt request flag
No interrupt request
Happens interrupt request
xxxIE
0
1
Interrupt enable flag
Disable interrupt
Enable interrupt
xxxLV1 xxxLV0 Interrupt level flag
This 2-bit flag sets the interrupt level by
assigning an interrupt level of 0 to 3 to
interrupt requests.
Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR,
SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W)
Interrupts 35