MN101C115 Datasheet, PDF (44/170 Pages) Panasonic Semiconductor – Request for your special attention and precautions in using the technical information and semiconductors described in this book

Chapter 2 Basic CPU Functions
2-3 Bus Interface
2-3-1 Overview
The MN101C117, unlike other MN101C series microcomputers, does not
support memory expansion mode and processor mode.
2-3-2 Control Registers
The memory control register is a four-bit register that sets up wait-count at a
time of access to a base address of interrupt vector table and a special
register zone.
(1) Memory control register(MEMCTR)
7
6
5
4
3
2
1
0
MEMCTR IOW1 IOW0 ^IVBA
IRWE
(at reset: 11001011)
Must be set to 11.
IRWE
0
1
Set software write for interrupt request flag
Software write disable
Even if data is written to each interrupt control
register (xxxICR), the state of the interrupt
request flag (xxxIR) will not change.
Software write enable
Must be set to 1.
Must be set to 0
30 Bus Interface
IVBA
0
1
Base address setting for interrupt vector table
Interrupt vector base = X'04000'
Interrupt vector base = X'00100'
IOW1 to 0
Number of wait cycles set when
accessing special register area
Bus cycle at
20MHz oscillation
00
No wait cycles
100ns
01
1 wait cycle
150ns
10
2 wait cycles
200ns
11
3 wait cycles
250ns
Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W