AND8090 Datasheet, PDF (9/20 Pages) ON Semiconductor – AC Characteristics of ECL Devices

AND8090/D
Differential Inputs (Single−Ended Mode) – Either input
of a differential pair may be used individually if the unused
input of the differential pair is connected to V_BB (the
switching reference voltage). The switching reference
voltage is provided by many differential devices. Figure 19
illustrates the use of the true input as the single−ended input.
Note that the unused inverted output is terminated in the
same fashion as the true output.
V_IH
50%
V_OH
50%
V_IL
D1
Q1 V_OL
D1
V_BB Q1 Use Q1 Termination
Figure 19. Differential Input in Single−Ended Mode
The switching reference voltage provides a switching
point that is approximately halfway between the HIGH and
LOW levels. As an example, the MC100EP116 data sheet
specifies the following switching reference voltage range
for the 5.0 V PECL mode. The MC100EP116 50% point
range previously calculated is listed below the V_BB range.
3475 mV v VBB v 3675 mV
3483 mV v 50% Point v 3748 mV
Note that the V_BB range is very close to the 50% point
range. This is true because the switching reference voltage
provides a switching point for a differential input in
single−ended mode that is analogous to the 50% point range
for normal single−ended inputs.
TIMING CHARACTERISTICS
Output Rise and Fall Times
ECL Output Devices – The output rise time for ECL
devices is the time required to rise from the 20% level to the
80% level of the output rising edge. The output fall time for
ECL devices is the time required to fall from the 80% level
to the 20% level of the output falling edge. The output rise
and fall times for devices with ECL outputs is shown in
Figure 20.
HIGH
80%
LOW
t_R
20%
t_F
Figure 20. ECL Output Rise and Fall Times
Non−ECL Output Devices – Refer to the translator data
sheets as different conditions are used to specify the output
rise and fall times. One type of condition specifies output
rise and fall times between the 10% and 90% output levels.
For example, the rise and fall times for the MC100ELT21
PECL to TTL translator are specified between the 10% and
90% output levels as shown in Figure 21.
HIGH
90%
LOW
t_R
10%
t_F
Figure 21. TTL Output Rise and Fall
Time Percentages
Another type of test condition specifies non−ECL output
rise and fall times between fixed output voltage levels. For
example, the rise and fall times for the MC100EPT21
LVPECL to LVTTL translator are specified between fixed
output voltages of 0.8 V and 2.0 V as shown in Figure 22.
HIGH
V_O = 2.0 V
LOW
t_R
V_O = 0.8 V
t_F
Figure 22. LVTTL Output Rise and Fall
Time Levels
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