AND8090 Datasheet, PDF (16/20 Pages) ON Semiconductor – AC Characteristics of ECL Devices

AND8090/D
As an example, the NBSG14 data sheet specifies the
typical Cycle−to−Cycle Jitter as 0.5 ps RMS which is the one
sigma value.
Total RJ Test Setup
The test setup shown in Figure 38 is used to sample edge
locations over a large number of periods, and then measure
the total RMS random jitter.
Pattern Generator
50% Duty
Cycle Pulse
DUT
50% Duty
Cycle Pulse
Trigger
Oscilloscope
RJ (RMS)
Total Jitter (RJ) + ^Ǹ[Pattern Generator (RJ)]2 ) [DUT (RJ)]2 ) [Oscilloscope (RJ)]2
Figure 38. Total Random Jitter Test
Test Equipment RJ Test Setup
The test setup shown in Figure 39 is used to measure the test equipment RMS random jitter.
Pattern Generator
50% Duty Cycle Pulse
Trigger
Oscilloscope
RJ (RMS)
Test Equipment Jitter (RJ) + ^Ǹ[Pattern Generator (RJ)]2 ) [Oscilloscope (RJ)]2
Figure 39. Test Equipment Random Jitter Test
DUT RJ Calculation
The DUT RMS random clock jitter determined with the following equation is specified as Cycle−to−Cycle Jitter.
DUT (RJ) + ^Ǹ[Total Jitter (RJ)]2 * [Test Equipment Jitter (RJ)] ²
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