AND8090 Datasheet, PDF (10/20 Pages) ON Semiconductor – AC Characteristics of ECL Devices

AND8090/D
Propagation Delay
Rising Edge Propagation – The rising edge (LOW−
to−HIGH transition) propagation delay (t_PLH or t_P++) is the
time needed to propagate an input rising edge to the output.
Falling Edge Propagation – The falling edge (HIGH−
to−LOW transition) propagation delay (t_PHL or t_{P− −}) is the
time needed to propagate an input falling edge to the output.
Single−Ended ECL Devices– Single−ended propagation
delay is measured between the 50% point of the input rising
or falling edge, and the 50% point of the identical output
edge. There are many types of single−ended propagation
delays such as a clock input to data output (CLK to Q)
propagation delay. Single−ended output propagation delay
is shown in Figure 23.
ECL Inputs and Non−ECL Outputs – Refer to the
device data sheet as several methods are used to measure the
output propagation delays. One method specifies the output
propagation delays from an ECL input crosspoint to a
non−ECL fixed output voltage. For example, the output
propagation delays for the MC100ELT21 PECL to TTL
translator are specified between the ECL input crosspoint
and a TTL output fixed voltage equal to 1.5 V as shown in
Figure 25.
IN
X_pt
X_pt
IN
50%
IN
50%
50%
OUT
t_PLH
t_PHL
50%
Figure 23. Single−Ended Propagation Delay
Differential ECL Devices – Differential propagation
delay is measured between the crosspoint of the input rising
or falling edge, and the crosspoint of the identical output
edge. There are many types of differential input/output pairs
such as inverted clock inputs to inverted data outputs (CLK
to Q). Differential output propagation delay is shown in
Figure 24.
IN
X_pt
X_pt
IN
OUT
X_pt
X_pt
OUT
t_PLH
t_PHL
Figure 24. Differential Propagation Delay
1.5 V
OUT
t_PLH
t_PHL
1.5 V
Figure 25. TTL Output Propagation Delay
Non−ECL Input and ECL Outputs – Refer to the device
data sheet as several methods are used to measure the output
propagation delays. One method specifies the output
propagation delays from a non−ECL input fixed voltage to
an ECL output 50% point. For example, the output
propagation delays for the MC10H352 CMOS to PECL
translator are specified between a CMOS input fixed voltage
equal to V_CC/2 and the ECL output 50% point as shown in
Figure 26.
V_CC/2
IN
V_CC/2
50%
50%
OUT
t_PLH
t_PHL
Figure 26. CMOS Input Propagation Delay
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