AND8090 Datasheet, PDF (14/20 Pages) ON Semiconductor – AC Characteristics of ECL Devices

AND8090/D
Negative Setup and Negative Hold Comment – The left
edge of the timing window is the setup edge, and the right
edge of the window is the hold edge. A negative setup time
with a negative hold time cannot occur as this principle
would be violated (i.e., the hold edge would occur before the
set edge).
Set and Reset Recovery Time
Applicability – Only devices with a Set input have set
recovery times (t_SR), and only devices with a Reset input
have reset recovery times (t_RR).
Measurement Points – Differential crosspoints (refer to
the “Differential Characteristics” section) and single−end
50% points (refer to the “Single−Ended Characteristics”
section) are used as time measurement points. Note from the
following figures that the 50% point of the active clock edge
is the time origin of all set and reset recovery time
measurements.
Minimum Set Recovery Time – This parameter defines
the minimum length of time that Set has to be inactive before
an active clock edge in order for the output to enter the
non−Set state. In the non−Set state, the output is no longer
dependent upon the Set state.
In the MC100EP29 example shown in Figure 35, the
minimum set recovery time of 150 ps specifies that the
system must be designed so that Set transitions from the
active HIGH state to the inactive LOW state at least 150 ps
before the active rising clock edge. The set recovery timing
requirement (150 ps) and the input setup time requirement
(100 ps) were both met in the example shown in Figure 35,
therefore the output transitions from the Set state (HIGH) to
the input state (LOW). The transition takes place after the
specified 420 ps HIGH−to−LOW CLK propagation delay.
Minimum Reset Recovery Time – This parameter
defines the minimum length of time that Reset has to be
inactive before an active clock edge in order for the output
to enter the non−Reset state. In the non−Reset state, the
output is no longer dependent upon the Reset state.
In the MC100EP29 example shown in Figure 36, the
minimum reset recovery time of 150 ps specifies that the
system must be designed so that Reset transitions from the
active HIGH state to the inactive LOW state at least 150 ps
before the active rising clock edge. The reset recovery
timing requirement (150 ps) and the input setup time
requirement (100 ps) were both met in the example shown
in Figure 36, therefore the output transitions from the Set
state (HIGH) to the input state (LOW). The transition takes
place after the specified 420 ps HIGH−to−LOW CLK
propagation delay.
50%
CLK
SET
50%
CLK
RESET
50%
50%
t_SR(ps)
INPUT
150
0
t_SR(min)
50%
t_s(ps)
OUTPUT
100
t_s(min)
t_PHL
420 ps
50%
Figure 35. Set Recovery Time Example
t_RR(ps)
0
150
t_RR(min)
INPUT
t_s(min)
OUTPUT
50%
100
t_s(min)
50%
t_PLH
420 ps
Figure 36. Reset Recovery Time Example
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