AND8090 Datasheet, PDF (8/20 Pages) ON Semiconductor – AC Characteristics of ECL Devices

AND8090/D
Differential Input Example – The relationship between
V_PP and V_IHCMR is used to completely define valid
differential input signals. The following MC100EP116
example is for the 5.0 V PECL mode (V_CC = 5.0 V, V_EE =
GND), and illustrates the valid input voltages for an
application which uses the minimum and maximum input
voltage swings for the device. Note that both the V_PP and the
V_IHCMR conditions are satisfied for each of the two
waveforms.
VIHCMR(min) + 2.0 V v VIH v VIHCMR(max) + 5.0 V
VPP(min) + 150 mV v VPP v VPP(max) + 1200 mV
The top waveform in Figure 15 represents the highest
possible LOW input value where:
VIL(max) + VIH(max) * VPP(min) + 5.0 * 0.15 + 4.85 V
The bottom waveform in Figure 15 represents the lowest
possible LOW input value where:
VIL(min) + VIH(min) * VPP(max) + 2.0 * 1.2 + 0.80 V
V_IHCMR(max) 5.0 V
D
4.8 V
D
V_IH = 5.0 V
V_PP = 0.15 V
V_IL = 4.85 V
3.0 V
V_IHCMR(min) 2.0 V
D
1.0 V
D
V_IH = 2.0 V
V_PP = 1.2 V
V_IL = 0.8 V
Figure 15. MC100EP116 Differential Input Voltage
SINGLE−ENDED CHARACTERISTICS
Section Note – This section explains concepts that only
apply to single−ended inputs and/or outputs.
Single−Ended Inputs – Many inputs/outputs are
single−ended instead of differential, i.e. they have a single
input/output instead of a pair of true and inverted
inputs/outputs.
Single−Ended 50% Points – Single−ended 50% points
are used as a measurement point for single−ended input and
output signals. A 50% point is the single−ended signal level
which lies halfway between the HIGH and LOW
input/output levels as shown in Figure 16.
V_IH or V_OH
50%
V_IL or V_OL
Figure 16. Single−Ended Input/Output 50% Point
Note from the following MC100EP116 calculations for
the 5.0 V PECL mode that the 50% point voltage is not a
fixed voltage. The 50% point varies with the input voltage
range.
50% Point(max) + [VIH(max) ) VIL(max)]ń2
+ (4120 ) 3375)ń2 + 3748 mV
50% Point(min) + [VIH(min) ) VIL(min)]ń2
+ (3775 ) 3190)ń2 + 3483 mV
Single−Ended Input Voltage Range – Single−ended
input HIGH and LOW levels have a boundary and a
threshold as shown in Figure 17. Once an input crosses a
logic threshold, the logic state is guaranteed to change to the
new state.
V_IHmax
HIGH
V_IHmin
Boundary
Threshold
V_ILmax
LOW
V_ILmin
Threshold
Boundary
Figure 17. Single−Ended Input Logic Levels
The MC100EP116 example shown in Figure 18 is for the
5.0 V PECL mode.
V_IHmax
HIGH
V_IHmin
4120 mV
3775 mV
V_ILmax
LOW
V_ILmin
3375 mV
3190 mV
Figure 18. MC100EP116 Single−Ended Input Example
Single−Ended Input Test Level – The AC test
single−ended input swing is typically given by the following
equation:
VIN(swing) + |VIH * VIL| + 750 mV
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