MT9P001 Datasheet, PDF (41/48 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9P001: 1/2.5-Inch 5Mp Digital Image Sensor
Electrical Specifications
I/O Timing
By default, the MT9P001 launches pixel data, FV and LV with the rising edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV and LV using the falling edge of
PIXCLK.
See Figure 30 and Table 18 for I/O timing (AC) characteristics.
Figure 30: I/O Timing Diagram
tR
tF
90%
10%
EXTCLK
tEXTCLK
PIXCLK
Data[7:0]
FRAME_VALID/
LINE_VALID
tCP
tPD
Pxl _ 0
tPFH
tPLH
tPD
Pxl _ 1
Pxl _ 2
FRAME_VALID leads LINE_VALID by 609 PIXCLKs.
*PLL disabled for ^tCP
tRP
tFP
90%
10%
Pxl _ n
tPFL
tPLL
FRAME_VALID trails
LINE_VALID by 16 PIXCLKs.
MT9P001_DS Rev. L 4/15 EN
41
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