MT9P001 Datasheet, PDF (15/48 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9P001: 1/2.5-Inch 5Mp Digital Image Sensor
Output Data Timing
Frame Time
The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array,
and is typically equal to 1 EXTCLK period. The sensor outputs data at the maximum rate
of 1 pixel per PIXCLK. One row time (^tROW) is the period from the first pixel output in a
row to the first pixel output in the next row. The row time and frame time are defined by
equations in Table 8.
Table 8:
Frame Time
Parameter
fps
t_FRAME
t_ROW
W
H
SW
HB
VB
HBMIN
VBMIN
t_PIXCLK
Name
Frame Rate
Frame Time
Row Time
Output Image Width
Output Image Height
Shutter Width
Horizontal Blanking
Vertical Blanking
Minimum Horizontal
Blanking
Minimum Vertical
Blanking
Pixclk Period
Equation
1/^tFRAME
(H + max(VB, VBMIN)) × ^tROW
2 × ^tPIXCLK x max(((W/2) + max(HB, HBMIN)),
(41 + 346 x (Row_Bin+1) + 99))
2 × ceil((Column_Size + 1) / (2 × (Column_Skip + 1)))
2 × ceil((Row_Size + 1) / (2 × (Row_Skip + 1)))
max (1, (2 * 16 × Shutter_Width_Upper)
+ Shutter_Width_Lower)
Horizontal_Blank + 1
Vertical_Blank + 1
346 × (Row_Bin + 1) + 64 + (WDC / 2)
max (8, SW - H) + 1
1/^fPIXCLK
Default Timing at
EXTCLK = 96 MHz
14
71.66ms
36.38s
2592 PIXCLK
1944 rows
1943 rows
1 PIXCLK
26 rows
450 PIXCLK
9 rows
10.42ns
Table 9:
The minimum horizontal blanking (HBMIN) values for various Row_Bin and
Column_Bin settings are shown in Table 9.
HB_MIN Values for Row_bin vs. Column_bin Settings
Row_
0
bin
1
3
Column_bin (WDC)
0
1
450
430
796
776
1488
1468
3
420
766
1458
MT9P001_DS Rev. L 4/15 EN
15
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