MT9P001 Datasheet, PDF (13/48 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9P001: 1/2.5-Inch 5Mp Digital Image Sensor
Output Data Timing
Output Data Timing
The output images are divided into frames, which are further divided into lines. By
default, the sensor produces 1944 rows of 2592 columns each. The FV and LV signals
indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a
clock to latch the data. For each PIXCLK cycle, one 12-bit pixel datum outputs on the
DOUT pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that
occur when FV is negated are called vertical blanking. PIXCLK cycles that occur when
only LV is negated are called horizontal blanking.
Figure 8: Default Pixel Output Timing
PIXCLK
FV
LV
DOUT[11:0]
P0 P1 P2 P3 P4 Pn
Vertical Blanking Horiz Blanking
Valid Image Data
Horiz Blanking Vertical Blanking
LV and FV
LV Format Options
The timing of the FV and LV outputs is closely related to the row time and the frame time.
FV will be asserted for an integral number of row times, which will normally be equal to
the height of the output image. If Show_Dark_Rows is set, the dark sample rows will be
output before the active image, and FV will be extended to include them. In this case,
FV’s leading edge happens at time 0.
LV will be asserted during the valid pixels of each row. The leading edge of LV will be
offset from the leading edge of FV by 609 PIXCLKs. If Show_Dark_Columns is set, the
dark columns will be output before the image pixels, and LV will be extended back to
include them; in this case, the first pixel of the active image still occurs at the same posi-
tion relative to the leading edge of FV. Normally, LV will only be asserted if FV is asserted;
this is configurable as described below.
The default situation is for LV to be negated when FV is negated. The other option avail-
able is shown in Figure 9 on page 14. If Continuous_LV is set, LV is asserted even when
FV is not, with the same period and duty cycle. If XOR_Line_Valid is set, but not Contin-
uous_Line_Valid, the resulting LV will be the XOR of FV and the continuous LV.
MT9P001_DS Rev. L 4/15 EN
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