MT9P001 Datasheet, PDF (21/48 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9P001: 1/2.5-Inch 5Mp Digital Image Sensor
Features
The DOUT, LV, FV, and STROBE outputs are launched on the rising edge of PIXCLK, and
should be captured on the falling edge of PIXCLK. The specific relationship of PIXCLK to
these other outputs can be adjusted in two ways. If Invert_Pixel_Clock is set, the sense of
PIXCLK is inverted from that shown in Figure 8 on page 13. In addition, if the pixel clock
has been divided by Divide_Pixel_Clock, it can be shifted relative to the other outputs by
setting Shift_Pixel_Clock.
PLL-Generated Master Clock
Note:
The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to
multiply the prescaler output, and another divider stage to generate the output clock.
The clocking structure is shown in Figure 13. PLL control registers can be programmed
to generate desired master clock frequency.
The PLL control registers must be programmed while the sensor is in the software
Standby state. The effect of programming the PLL divisors while the sensor is in the
streaming state is undefined.
Figure 13: PLL-Generated Master Clock
PLL Input Clock PLL Output Clock
EXTCLK
Pre PLL
Div
(PFD)
N
PLL_n_divider +1
PLL
Multiplier
(VCO)
M
PLL_m_factor
PLL
Output
Div 1
P1
PLL_p1_divider +1
SYSCLK (PIXCLK)
PLL Setup
The MT9P001 has a PLL which can be used to generate the pixel clock internally.
To use the PLL:
1. Bring the MT9P001 up as normal, make sure that ^fEXTCLK is between 6 and 27 MHz
and then power on the PLL by setting Power_PLL (R0x10[0] = 1).
2. Set PLL_m_Factor, PLL_n_Divider, and PLL_p1_Divider based on the desired input
(^fEXTCLK) and output (^fPIXCLK) frequencies. Determine the M, N, and P1 values to
achieve the desired ^fPIXCLK using this formula:
f_{PIXCLK = (}f_{EXTCLK × M) / (N × P1)}
where
M = PLL_m_Factor
N = PLL_n_Divider + 1
P1 = PLL_p1_Divider + 1
Note:
If P1 is odd (that is, PLL_p1_Divider is even), the duty cycle of the internal system
clock will not be 50:50. In this case, it is important that either a slower clock is used or
all clock enable bits are set in R101.
MT9P001_DS Rev. L 4/15 EN
21
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