AMIS-30421 Datasheet, PDF (33/41 Pages) ON Semiconductor – Micro-Stepping Stepper Motor Bridge Controller

AMIS−30421
Table 16. CONTROL REGISTER 2 PARAMETERS
Parameter
Value
Value
Description
Info
0
No additional offset
SLA_OFFS
1
Additional offset of
To enable an additional offset on the SLA−pin of 0.6V.
p20
0.6 V
Remark: Bit 5 of Control Register 2 should always be ‘0’ (zero)!
Status Register 0 (SR0)
Status Register 0 is located at address 0x04 and can only be read. Status Register 0 is a non−latched register meaning that
the value of the register can change without the need of reading out the register. The register can be used to retrieve the
temperature range or to verify a watchdog event.
Notice that bit 7 is the parity bit (see READ operation p26).
Table 17. STATUS REGISTER 0
Address
0x04
Access
Reset
Data
Bit 7
R
0
PAR
Status Register 0 (SR0)
Bit 6
Bit 5
Bit 4
R
R
R
0
0
0
TR[1:0]
WD
Bit 3
R
0
−
Bit 2
R
1
−
Bit 1
R
0
−
Bit 0
R
0
−
Table 18. STATUS REGISTER 0 PARAMETERS
Parameter
Value
Value
00
−40°C to 15°C
01
15°C to 72°C
TR[1:0]
10
73°C to 150°C
TSD = 0: 150°C to 170°C
11
TSD = 1: >170°C
0
No watchdog event
WD
1
Watchdog event occurred
Description
Motor driver thermal range.
Remark:
TR[1:0] = 11 and TSD = 0 => Thermal Warning
TR[1:0] = 11 and TSD = 1 => Thermal Shutdown
TSD is located in Status Register 2
If WDEN = 1 and watchdog not acknowledged before the
Watchdog Time−out (WDT[3:0]), WDb−pin will be pulled
low for 100ms to reset an external microcontroller and WD
bit will be set to ‘1’ to indicate this event. The external mi-
crocontroller can use this bit to verify a cold (WD = 0) or
warm boot (WD = 1).
Info
p23
p24
Status Register 1 (SR1)
Status Register 1 is located at address 0x05 and can only be read. Status Register 1 is a latched register. If an error occurs
the bit will be set and can only be cleared by reading out this bit¹. The register is used to report an overcurrent or open coil in
the X−coil, or to report a charge pump failure.
Notice that bit 7 is the parity bit (see READ operation p26).
Table 19. STATUS REGISTER 1
Address
0x05
Access
Reset
Data
Bit 7
R
0
PAR
Status Register 1 (SR1)
Bit 6
Bit 5
Bit 4
R
R
R
0
0
0
OVCXPT OVCXPB OVCXNT
Bit 3
R
0
OVCXNB
Bit 2
R
0
CPFAIL
Bit 1
R
0
OPEN_X
Bit 0
R
0
−
1. In Sleep mode the register can be read out but will not be cleared!
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