AMIS-30421 Datasheet, PDF (26/41 Pages) ON Semiconductor – Micro-Stepping Stepper Motor Bridge Controller

AMIS−30421
SPI INTERFACE
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
AMIS−30421. The implemented SPI block is designed to
interface directly with numerous microcontrollers from
several manufacturers. AMIS−30421 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
DO signal is the output from the Slave (AMIS−30421), and
DI signal is the output from the Master. A chip select line
(CSb) allows individual selection of a Slave SPI device in a
multiple−slave system. The CSb line is active low. If
AMIS−30421 is not selected, DO is in HiZ and does not
interfere with SPI bus activity. The output type of DO can be
set in SPI (<IO_OT>). Since AMIS−30421 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
8
7
6
5
4
3
2
1
CS
ÏÏÏÏÏÏÏÏ ^CLK
DI
MSB
6
5
4
3
2
1
DO
MSB
6
5
4
3
2
1
Figure 24. Timing Diagram of a SPI Transfer
LSB
LSB
ÏÏÏÏÏÏÏÏÏÏ
Transfer Packet
Serial data transfer is assumed to follow MSB first rule.
The transfer packet contains one or more bytes.
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30421 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30421 in a READ operation.
Two command types can be distinguished in the
communication between master and AMIS−30421:
• CMD2 = ‘0’: READ from SPI Register with address
ADDR[4:0]
• CMD2 = ‘1’: WRITE to SPI Register with address
ADDR[4:0]
BYTE1
Command and SPI Register Address
BYTE2
Data
MSB
LSB
MSB
LSB
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Command
SPI Register Address
Figure 25. SPI Transfer Packet
READ Operation
If the Master wants to read data from a Status or Control
Register, it initiates the communication by sending a READ
command. This READ command contains the address of the
SPI register to be read out. At the falling edge of the eight
clock pulse the data−out shift register is updated with the
content of the corresponding internal SPI register. In the next
8−bit clock pulse train this data is shifted out via DO pin. At
the same time the data shifted in from DI (Master) should be
interpreted as the following successive command or dummy
data.
Status Register 0, 1 and 2 (see SPI Registers) contain 7
data bits and a parity check bit. The most significant bit (D7)
represents a parity of D[6:0]. If the number of logical ones
in D[6:0] is odd, the parity bit D7 equals ‘1’. If the number
of logical ones in D[6:0] is even then the parity bit D7 equals
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