TDA6650ATT Datasheet, PDF (8/54 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Linked to this noise improvement, some disturbances may become visible while they were
not visible because they were hidden into the noise in analog dedicated applications and
circuits.
This is especially true for disturbances coming from the I²C-bus traffic, whatever this traffic
is intended for the MOPLL or for another slave on the bus.
To avoid this I²C-bus crosstalk and be able to have a clean noise spectrum, it is necessary
to use a bus gate that enables the signal on the bus to drive the MOPLL only when the
communication is intended for the tuner part (such a kind of I²C-bus gate is included into
the NXP terrestrial channel decoders), and to avoid unnecessary repeated sending of the
same information.
8. I²C-bus protocol
The TDA6650ATT; TDA6651ATT is controlled via the two-wire I²C-bus. For programming,
there is one device address (7 bits) and the R/W bit for selecting read or write mode. To be
able to have more than one MOPLL in an I²C-bus system, one of four possible addresses
is selected depending on the voltage applied to address selection pin AS (see Table 8).
The TDA6650ATT; TDA6651ATT fulfils the fast mode I²C-bus, according to the NXP
I²C-bus specification, except for the timing as described in Figure 4. The I²C-bus interface
is designed in such a way that the pins SCL and SDA can be connected to 5 V, 3.3 V
or to 2.5 V pulled-up I²C-bus lines, depending on the voltage applied to pin BVS (see
Table 5).
8.1 Write mode; R/W = 0
After the address transmission (first byte), data bytes can be sent to the device (see
Table 6). Five data bytes are needed to fully program the TDA6650ATT; TDA6651ATT.
The I²C-bus transceiver has an auto-increment facility that permits programming the
device within one single transmission (address + 5 data bytes).
The TDA6650ATT; TDA6651ATT can also be partly programmed on the condition that the
first data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The
first bit of the first data byte transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I²C-bus STOP condition is sent by the controller, additional
data bytes can be entered without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission (STOP condition). Each control
byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider
data are valid only if no new I²C-bus transmission is started (START condition) during the
computation period of 50 µs.
Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the
ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in
the same transmission.
TDA6650ATT_6651ATT_2
Product data sheet
Rev. 02 — 2 February 2007
© NXP B.V. 2007. All rights reserved.
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