TDA6650ATT Datasheet, PDF (10/54 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
8.1.1 I²C-bus address selection
The device address contains programmable address bits MA1 and MA0, which offer the
possibility of having up to four MOPLL ICs in one system. Table 8 gives the relationship
between the voltage applied to the AS input and the MA1 and MA0 bits.
Table 8. Address selection
Voltage applied to pin AS
0 V to 0.1V_CC
0.2V_CC to 0.3V_CC or open-circuit
0.4V_CC to 0.6V_CC
0.9V_CC to V_CC
MA1
0
0
1
1
MA0
0
1
0
1
8.1.2 XTOUT output buffer and mode setting
The crystal frequency can be sent to pin XTOUT and used in the application, for example
to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of
material. To output f_xtal, it is necessary to set T[2:0] to 001. If the output signal on this pin
is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used
to output ¹â„₂f_div and f_comp in a test mode. At power-on, the XTOUT output buffer is set to
on, supplying the f_xtal signal. The relation between the signal on pin XTOUT and the
setting of the T[2:0] bits is given in Table 9.
Table 9.
T2
0
0
0
0
1
1
1
1
XTOUT buffer status and test modes
T1
T0
Pin XTOUT
0
0
disabled
0
1
f_xtal (4 MHz)
1
0
1_⁄2fdiv
1
1
f_xtal (4 MHz)
0
0
f_comp
0
1
1_⁄2fdiv
1
0
f_xtal (4 MHz)
1
1
disabled
Mode
normal mode with XTOUT buffer off
normal mode with XTOUT buffer on
charge pump off
not used^[1]
test mode
test mode
charge pump sinking current^[2]
charge pump sourcing current
[1] This is an on-chip function that automatically sets internal values for the PLL. This function is not optimized
for ISDB-T and NTSC Japan and therefore must not be used.
[2] This is the default mode at power-on reset. This mode disables the tuning voltage.
8.1.3 Step frequency setting
The step frequency is set by three bits, giving five steps to cope with different application
requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The
phase detector works at either 4 MHz, 2 MHz or 1 MHz.
Table 10 shows the step frequencies and corresponding reference divider ratios. When
the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes
DB1 and DB2.
TDA6650ATT_6651ATT_2
Product data sheet
Rev. 02 — 2 February 2007
© NXP B.V. 2007. All rights reserved.
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