TDA6650ATT Datasheet, PDF (12/54 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 12.
CP2
1
1
1
Charge pump current …continued
CP1
CP0
Charge pump current
number
0
1
6
1
0
7
1
1
8
Typical current (absolute
value in µA)
254
400
580
8.2 Read mode; R/W = 1
Data can be read from the device by setting the R/W bit to 1 (see Table 13). After the
device address has been recognized, the device generates an acknowledge pulse and the
first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the
SDA line during a HIGH level of the SCL clock signal.
A second data byte can be read from the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End of transmission will occur if no
master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
Table 13. I²C-bus read data format
Name
Byte Bit
Ack
MSB^[1]
LSB
Address byte 1
1
1
0
0
0
MA1 MA0 R/W = 1 A
Status byte 2
POR
FL 0
1
AGC A2 A1 A0
-
[1] MSB is transmitted first.
Table 14. Description of read data format bits
Bit
Description
A
acknowledge
POR
power-on reset flag
POR = 0, normal operation
POR = 1, power-on reset
FL
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
AGC
internal AGC flag
A2, A1, A0
AGC = 0 when internal AGC is active (V_AGC < V_RML)
AGC = 1 when internal AGC is not active (V_AGC > V_RMH)
digital outputs of the 5-level ADC; see Table 15
Table 15. ADC levels
Voltage applied to pin ADC^[1]
0.6V_CC to V_CC
0.45V_CC to 0.6V_CC
A2
A1
A0
1
0
0
0
1
1
TDA6650ATT_6651ATT_2
Product data sheet
Rev. 02 — 2 February 2007
© NXP B.V. 2007. All rights reserved.
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