TDA8295 Datasheet, PDF (65/77 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
13.3 DAC connection
This DAC has a differential current output capable of driving a doubly terminated 75 Ω
transmission line without external buffers. But it can also be used in single-ended
applications. In that case both outputs still need proper termination. The off-chip resistive
load must be connected to ground.
With the B_DA_V and B_DA_S coarse output level adjustment registers, the output
current can be increased (linearly) up to two times. However, the maximum output voltage
at both V_IOUTP, V_IOUTN and S_IOUTP, S_IOUTN output nodes still is 1.5 V.
DNL and INL increase when the external biasing resistor is increased. When higher load
resistances are used, distortion will increase linearly. About 12 dB increase in harmonic
distortion is expected at 150 Ω.
Several measures can be taken in order to reach good performance. Decouple the
V_{DDA(DAC1)(3V3)} and the V_{DDA(DAC2)(3V3)} supplies with at least 100 nF. Place the external
bias resistor close to the chip. Do not add decoupling capacitance to pin RSET.
The following relation gives the value of the full-scale current I_FS in function of the bias
resistance value, FineControl (B_REF) and CoarseControl (B_DA_V or B_DA_S):
I_FS = _R-¹---^.S-²--_E-¹---_T6-- × ₁----₀---₀----_–-----_F--¹-_i--_n0---_e0---_C----_o---_n---_t-_r---_o---_l × ¹⁵-- × ⁶----⁴----⁺-----^C----^o---^a--₄-^r--_8s---^e--^C----^o---ⁿ---^t--^r--^o---^l × 64
(1)
−7 ≤ FineControl ≤ +7
0 ≤ CoarseControl ≤ 63
For programming of FineControl (B_REF) see Table 55, for CoarseControl signals
B_DA_V see Table 53, for B_DA_S see Table 54.
13.4 ADC connection
The input signals of the ADC (IF_POS and IF_NEG) can be either AC coupled by means
of two capacitors or connected directly to the inputs (DC coupled). This selection is done
by programming of DCIN, see Table 51.
In case of AC coupling, DCIN should be set to logic 0, which enables two resistive dividers
between V_{DDA(ADC)(3V3)} and V_SSD1 take care of the correct DC biasing of the input signals.
In case only a single-ended input signal is available, this signal should be connected to
the IF_POS input by means of a coupling capacitor whereas the IF_NEG input should be
connected to ground using a similar capacitor.
In case the input signal is DC coupled, the input resistor network can be switched off by
setting the DCIN bit to logic 1. When using the ADC in this mode, the Common mode level
of the input signals should be at 0.5 × V_{DDA(ADC)(3V3)}. In case of single-ended operation,
the input signal should be connected directly to the IF_POS input and the IF_NEG input
should be connected to a voltage equal to the Common mode level of the input signal
(0.5 × V_{DDA(ADC)(3V3)}).
The peak-to-peak input range can be set to 1 V (p-p) or 2 V (p-p) by programming of
GAINSET (see Table 51). With a differential input the performances of the ADC are
slightly better with GAINSET = 0 whereas with a single-ended input they are slightly better
with GAINSET = 1.
TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
© NXP B.V. 2008. All rights reserved.
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