TDA8295 Datasheet, PDF (43/77 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
9.3.17 ADC control
In the TDA8295 a 12-bit ADC is implemented sampling with a 54 MHz clock (27 MHz
optional).
Table 51. ADC_CTL register (address 33h) bit description
Legend: * = default value.
Bit Symbol Access Value Description
7
GAINSET R/W
The track and hold circuit in the converter has a
programmable gain setting, which is controlled by the
GAINSET parameter. In case the gain of the track and hold is
increased, the input range of the ADC is decreased
accordingly.
0*
2.0 V (p-p)
1
1.0 V (p-p) (6 dB gain)
6 to 4 CS[2:0] R/W
The current consumption of the ADC can be programmed
with these two bits. It is possible to increase or decrease the
current by the following ratio:
000
not allowed
001
not allowed
010*
0.50 (recommended for 54 MHz sampling)
011
0.75
100
1.00
101
1.25
110
1.50
111
not allowed
3
DCIN
R/W
The input signal of the ADC can be either AC coupled by
means of two capacitors or connected directly to the inputs
(DC coupled).
0*
AC coupling
1
DC coupling
2
TWOS R/W
This parameter controls the output format of the ADC.
0
offset binary format
1*
twos complement format
1
SLEEP R/W
When HIGH, SLEEP sets the ADC into its Sleep mode. Both
bias current and clock are switched off. In this mode, the
current consumption is reduced by a factor of 6. The
reference circuit will remain active in order to guarantee a fast
recovery from Sleep mode.
0*
Normal mode
1
ADC Sleep mode
0
PD_ADC R/W
When HIGH, PD_ADC sets the ADC into its Power-down
mode. All internal currents are switched off. In this mode, the
current consumption is near zero (leakage current only).
0*
Normal mode
1
ADC Power-down mode
TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
© NXP B.V. 2008. All rights reserved.
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