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TDA8295 Datasheet, PDF (47/77 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio
NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
Table 58. PLL_REG06 register (address 3Eh) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7
-
R/W 0
reserved, must be set to logic 0
6
CLK_EN
R/W
CLK_EN controls the PLL output clock
0
PLL output clock disable
1*
PLL output clock enable
X
don’t care if PLL_AUTO = 1
5
BYP_PLL
R/W
When HIGH, the internal clocks (for logic, ADC, and
DACs) are directly controlled by the pin XIN.
BYP_PLL acts both on external multiplexers and on
internal PLL bypass. When PLL initialization is
automatic (PLL_AUTO = 1), BYP_PLL is not
considered.
0
internal clocks are controlled by PLL clock
1*
internal clocks are controlled by pin XIN
X
don’t care if PLL_AUTO = 1
4
DIRECTO
R/W 0*
When DIRECTI is set to logic 1, the pre-divider is
3
DIRECTI
R/W 0*
bypassed. If DIRECTO is equal to logic 1, then it is
the post-divider, which is bypassed. Please see
Table 59 for further details.
2 and 1 -
R/W 00
reserved, must be set to logic 00
0
PD_PLL
R/W
Put the PLL in Power-down mode if equal to logic 1.
When PLL initialization is automatic
(PLL_AUTO = 1), PD_PLL is not considered.
0
PLL active
1*
PLL Power-down mode
X
don’t care if PLL_AUTO = 1
Table 59. Truth table for PLL output clock frequency
Legend: * = default value.
DIRECTI
DIRECTO
PLL output clock frequency[1]
1
1
1
0
fclk(o)(PLL) = fVCO = fi × 2 × M
f clk(o)(PLL) = -2f---V-×--C---PO-- = -f---i---×P-----M---
0
1
f clk(o)(PLL) = f VCO = -f---i---×----N-2----×-----M----
0*
0*
f clk(o)(PLL) = -2f---V-×--C---PO-- = -f-N--i---×-×----MP---
[1] For description of M, N and P see Table 60.
For optimum performances, the following relations must be respected:
• 275 MHz ≤ fVCO ≤ 550 MHz
• 4 kHz ≤ fi ≤ 150 MHz if DIRECTI = 1, else 4 kHz ≤ fi / N ≤ 150 MHz
TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
© NXP B.V. 2008. All rights reserved.
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