TDA8295 Datasheet, PDF (42/77 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
Table 49. CLB_STDBY register (address 30h) bit description
Legend: * = default value.
Bit Symbol Access Value Description
7 to 2 -
R/W -
not used
1
STDBY R/W
When STDBY is set to logic 1, the chip enters in Standby
mode, and its power consumption is reduced. The IF AGC pin
is set to high-ohmic. The default value is logic 0, which means
that the chip is active.
0*
Normal mode
1
Standby mode
0
CLB R/W
This signal clears the TDA8295 through the I²C-bus interface
(software reset). To activate the reset, just write CLB = 0. This
software reset will not affect the content of the registers.
0
activate soft reset
1*
normal operation
9.3.16 Status of clock PLL and video/sound DAC load
Table 50. ANALOG_STAT register (address 32h) bit description
Bit Symbol
Access Value Description
7
-
R
-
not used
6
LOAD_DACV R
output load identification video DAC
0
Normal mode
1
If active, the video DAC output voltage is above
reference voltage.
5
LOAD_DACS R
output load identification sound DAC
0
Normal mode
1
If active, the sound DAC output voltage is above
reference voltage.
4
PLL_LOCK R
clock PLL lock indicator
0
clock PLL unlocked
1
indicates that the clock PLL is locked
3 to 0 -
R
-
reserved
TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
© NXP B.V. 2008. All rights reserved.
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