TDA8295 Datasheet, PDF (46/77 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
9.3.19 Clock generation (PLL and crystal oscillator)
The TDA8295 implements a crystal oscillator which can be used either in Slave mode or
in Oscillator mode (see Section 13.7), and a multipurpose PLL which receives XIN as
input clock, and delivers the system clock of the IC (108 MHz).
Table 56. PLL_REG00 register (address 38h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 and 6 -
R/W 00
reserved, must be set to logic 00
5
PLL_AUTO R/W
clock PLL mode control
0
The sequencing of the programming and monitoring
of the PLL can be made ‘manually’ through CLK_EN,
BYP_PLL, PD_PLL and LOCK, according to the
following set of instructions:
After a hardware reset:
• Set PLL_AUTO to logic 0
• By default, CLK_EN = BYP_PLL = PD_PLL = 1,
LOCK = 0, the PLL is in Power-down mode, is not
locked, and the output clock is the clock of the
quartz oscillator used to resynchronize reset
signals in the TDA8295
Then:
• Set BYP_PLL and CLK_EN to logic 0
• Set MSEL, NSEL and PSEL that are
corresponding to the frequency required value
• Set PD_PLL to logic 0, in order that the PLL
takes those parameters into account and starts
up
• Then, wait for a minimum time of 500 µs (which is
the maximum time the PLL should take to lock).
This time could be used to make the
programming of the other I²C-bus registers.
• Set CLK_EN to logic 1 to enable the sampling
frequency to the rest of the chip
• Optionally, verify that LOCK = 1
1*
The sequencing of the programming and monitoring
of the PLL is handled automatically by the TDA8295
at initialization and each time one of the M, N, P
parameters is changed. Thus, the user has only to
program M, N, P and then once the PLL is locked, its
output clock becomes enabled automatically.
4 to 0 -
R/W 0 0000 reserved, must be set to logic 0 0000
Table 57. PLL_REG04 register (address 3Ch) bit description
Bit
Symbol
Access Value Description
7 to 3 -
R/W -
not used
2 to 0 -
R/W 000
reserved, must be set to logic 000
TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
© NXP B.V. 2008. All rights reserved.
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