TDA8295_09 Datasheet, PDF (55/83 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

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Table 68. CVBS_EQ_COEFx_LOW and CVBS_EQ_COEFx_HIGH (x = 0 to 5) register (address 57h to 62h) bit description
Legend: * = default value^[1].
Address Register
Bit Symbol
Access Value Description
57h
CVBS_EQ_COEF0_LOW 7 to 0 CVBS_EQ_COEF0[7:0] R/W 00h* The overall video (CVBS) equalizer is a symmetric FIR filter with
58h
CVBS_EQ_COEF0_HIGH 7 to 4 -
R/W -
11 taps. Due to the symmetry the group delay is constant (linear
3 to 0 CVBS_EQ_COEF0[11:8] R/W 0h* ^{phase). The transfer function is as follows, while the sampling rate is}
13.5 MHz:
59h
CVBS_EQ_COEF1_LOW 7 to 0 CVBS_EQ_COEF1[7:0] R/W 00h*
5Ah
CVBS_EQ_COEF1_HIGH 7 to 4 -
R/W -
H(z) = h₀ + h₁ × z^–1 + h₂ × z^–2 + h₃ × z^–3 + h₄ × z^–4 + ... + h₁₀ × z^–10
3 to 0 CVBS_EQ_COEF1[11:8] R/W 0h* ^{Please note that because of the symmetry h0 = h10, h1 = h9, h2 = h8,}
5Bh
CVBS_EQ_COEF2_LOW 7 to 0 CVBS_EQ_COEF2[7:0] R/W
00h* ^{h3 = h7 and h4 = h6. The mid coefficient h5 is only present once.}
CVBS_EQ_COEFx (x = 0 to 5) are defining the coefficients, i.e.
5Ch
CVBS_EQ_COEF2_HIGH 7 to 4 -
R/W -
CVBS_EQ_COEF0 = h₀ = h₁₀, CVBS_EQ_COEF1 = h₁ = h₉,
3 to 0 CVBS_EQ_COEF2[11:8] R/W
0h* _{CVBS_EQ_COEF2 = h2 = h8, CVBS_EQ_COEF3 = h3 = h7,}
5Dh
CVBS_EQ_COEF3_LOW 7 to 0 CVBS_EQ_COEF3[7:0] R/W 00h* _{CVBS_EQ_COEF4 = h4 = h6 CVBS_EQ_COEF5 = h5. Each of the}
5Eh
CVBS_EQ_COEF3_HIGH 7 to 4 -
R/W -
coefficients h₀ to h₅ has got 12-bit quantization. The coefficients are in
3 to 0 CVBS_EQ_COEF3[11:8] R/W 0h* signed fixed-point format, the representation is in two’s complement.
5Fh
CVBS_EQ_COEF4_LOW 7 to 0 CVBS_EQ_COEF4[7:0] R/W 00h* ^{There is one sign bit, one magnitude bit and 10 fractional bits. Each}
60h
CVBS_EQ_COEF4_HIGH 7 to 4 -
R/W -
fractional bit represents an inverse power of two, so that the highest
value for a coefficient is 2⁰ + 2^−1 + ... + 2^−10 = 2¹ − 2^−10 =
3 to 0 CVBS_EQ_COEF4[11:8] R/W
0h* _{1.9990234375. The binary representation for this value is}
61h
CVBS_EQ_COEF5_LOW 7 to 0 CVBS_EQ_COEF5[7:0] R/W 00h* _{01.11 1111 1111 (= 7FFh) and all bits except the sign bit are logic 1. As}
62h
CVBS_EQ_COEF5_HIGH 7 to 4 -
R/W -
two’s complement is chosen, the lowest value for a coefficient is −2,
3 to 0 CVBS_EQ_COEF5[11:8] R/W
4h* ^{which is 10.00 0000 0000 (= 800h) in the binary representation. So, for}
the lowest possible value, only the sign bit is logic 1. The shown
default values for CVBS_EQ_COEFx (x = 0 to 5) implement a flat
equalizer response.
[1] Don’t care if CVBS_EQ_CTRL = 0; see Table 36.
Example of Table 68: If an attenuation of around 1 dB for video frequencies greater than 2 MHz is wanted, the following
figure (see Figure 13) can be implemented.