TDA8295_09 Datasheet, PDF (12/83 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
The above wideband, slowly acting AGC loop (uncorrelated) is of first-order integral
action. It is closed via the continuous tuner IF AGC amplifier in the Silicon Tuner via a
bit stream DAC (PWM signal at 13.5 MHz, 27 MHz or 54 MHz) and an external and
uncritical first-order RC low-pass.
8.8 Digital IF AGC
Common to both IF AGC concepts is the peak search algorithm as long as the H/V PLL is
not locked. This is of advantage for the acquisition by avoiding hang-ups due to excessive
overloading, so being able to leave the saturated condition by reducing the gain.
Two Detection modes are made available in the IC via I²C-bus.
• Black level gated AGC:
The first mode uses an IF AGC detector which is gated with a very robust and
well-proven H/V sync PLL block on board. Gating occurs on the black level (most of
the time on the back porch) of the video signal and the control is delivered after an
error integration and exponential weighting to the internal IF AGC amplifier. This
IF AGC amplifier, in fact a multiplier, has a control range of −20 dB to +48 dB.
• Peak AGC:
A fast attack and slow decay action cares for a good and nearly clip-free transient
behavior. This proved to be more robust for non-standard signals, like sync clipping
along the transmitter/receiver chain.
With respect to the IF AGC speed generally, only the gated black level or peak sync
IF AGC can be made fast. However the peak search one, used for positive
modulation standards (L and L-accent standard), is rather slow because the VITS is
present only once in a field.
The correlated or narrow-band AGC loop, closed via the continuous IF AGC amplifier
in the TDA8295, is of first-order integral action and settles at a constant IF input level
with a permanent headroom of 12 dB (picture carrier). This headroom is needed for
the own sound carriers and the leaking neighbor (N − 1) spectrum.
8.9 Clock generation
Finally, either an external reference frequency (i.e. from the Silicon Tuner) or an own
on-chip crystal oscillator in the TDA8295 feeds the internal PLL synthesizer to generate
the necessary clock signals.
9. I²C-bus control
9.1 Protocol of the I²C-bus serial interface
The TDA8295 internal registers are accessible by means of the I²C-bus serial interface.
The SDA bidirectional pin is used as the data input/output pin and SCL as the clock input
pin. The highest SCL speed is 400 kHz.
TDA8295_C2_2
Product data sheet
Rev. 02 — 27 November 2009
© NXP B.V. 2009. All rights reserved.
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