TDA8295_09 Datasheet, PDF (50/83 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
Table 60. PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description
Legend: * = default value.
Address Register Bit Symbol Access Value Description
3Fh
PLL_REG07 7
-
R/W -
not used
6 to 0 -
R/W 00h reserved, must be set to 00h
40h
PLL_REG08 7 to 0 MSEL[7:0] R/W 1Ah* It programs the M parameter (M = MSEL + 1). M is the PLL
feedback-divider.
41h
PLL_REG09 7 to 1 NSEL[6:0] R/W 01h* It programs the N parameter (N = NSEL + 1). N is the PLL
pre-divider.
0
-
R/W 0
reserved, must be set to logic 0
42h
PLL_REG10 7 to 5 -
R/W 000 reserved, must be set to logic 000
4 to 0 PSEL[4:0] R/W
01h* It programs the P parameter (P = PSEL + 1). P is the PLL
post-divider.
Table 61. XTALOSC_CTL register (address 43h) bit description
Legend: * = default value.
Bit
Symbol Access Value Description
7 to 3 -
R/W -
not used
2
HF
R/W
With HF, the transconductance of the oscillator gain stage can be set. For
f_XIN > 20 MHz, HF should be set to logic 1.
0*
recommended for standard application (16 MHz)
1 and 0 -
1
recommended if f_XIN > 20 MHz
R/W 00 reserved, must be set to logic 00
TDA8295_C2_2
Product data sheet
Rev. 02 — 27 November 2009
© NXP B.V. 2009. All rights reserved.
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