NT3H2111 Datasheet, PDF (25/77 Pages) NXP Semiconductors – Designed to be the perfect enabler for NFC in home-automation

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
Table 10. …continuedPassword and Access Configuration bytes
Bit Field
Access Access Default
via NFC via I²C values
Description
3 2K_PROT
R&W R&W 0b
Password protection for Sector 1 for 2k version
0b: password authentication for Sector 1 disabled
1b: password authentication needed to access Sector 1
2 SRAM_PROT R&W R&W 0b
Password protection for pass-through and mirror mode
0b: password authentication for pass-through mode disabled
1b: password authentication needed to access SRAM in
pass-through mode
1-0 I2C_PROT
R&W R&W 00b
Access to protected area from I²C perspective
00b: Entire user memory accessible from I²C
01b: read and write access to unprotected user area, read only
access to protected area
1Xb: read and write access to unprotected area, no access to
protected area.
Note: Independent from these bits I²C has always R/W access
to:
• Session registers
• SRAM
• Configuration pages including PWD Configuration area, but
dependent on REG_LOCK_I2C bit
8.3.12 NTAG I²C configuration and session registers
NTAG I²C plus behavior can be configured and read in two separate locations depending
if the configurations shall be effective within the communication session (use session
registers) or by default after Power-On Reset (POR) (use configuration registers).
The configuration registers of pages E8h to E9h (Sector 0 - see Table 11) via the NFC
interface or block 3Ah via the I²C interface are used to configure the default behavior of
the NTAG I²C plus. Those bit values are stored in the EEPROM and represent the default
settings to be effective after POR. Their values can be read and written by both interfaces
when applicable and when not locked by the register lock bits (see REG_LOCK in
Table 13).
Table 11. Configuration register NTAG I²C plus
NFC address I²C Address
(Sector 0)
Byte number from NFC perspective
Dec Hex Dec Hex
0
1
2
232 E8h 58 3Ah
NC_REG
LAST_NDEF_BLOCK SRAM_MIRROR_BLOCK
233 E9h
WDT_MS
I2C_CLOCK_STR
REG_LOCK
3
WDT_LS
RFU
The session register on pages ECh to EDh (Sector 0) via the NFC interface or block FEh
via I²C, see Table 12, are used to configure or monitor the values of the current
communication session. Those bits are read only via the NFC interface but may be read
and written via the I²C interface.
For backward compatibility reasons the session registers are mirrored to Sector 3 (page
F8h and F9h via the NFC interface).
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
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