LMH1982 Datasheet, PDF (9/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

Application Information
1.0 FUNCTIONAL OVERVIEW
The LMH1982 is an analog phase locked loop (PLL) clock
generator that can output simultaneous SD and HD video
clocks synchronized or “genlocked” to H sync and V sync in-
put reference timing. The LMH1982 features an output Top of
Frame (TOF) pulse generator with programmable timing that
can also be synchronized to the reference frame. Two refer-
ence ports are provided to allow a secondary input to be
selected.
The clock generator uses a two-stage PLL architecture. The
first stage is a VCXO-based PLL (PLL 1) that requires an ex-
ternal 27 MHz VCXO and loop filter. In Genlock mode, PLL 1
can phase lock the VCXO clock to the input reference after
programming the PLL divider ratio. The use of a VCXO pro-
vides a low phase noise clock source even when the
LMH1982 is configured with a low loop bandwidth, which is
necessary to attenuate input timing jitter for minimum jitter
transfer. The combination of the external VCXO, external loop
filter, and programmable PLL parameters can provide flexi-
bility for the system designer to optimize the loop bandwidth
and loop response for the application.
The second stage consists of three PLLs (PLL 2, 3, 4) with
integrated VCOs and loop filters. These PLLs will attempt to
continually track the reference VCXO clock phase from
PLL 1 regardless of the device mode. The second stage PLLs
have pre-configured divider ratios to provide frequency mul-
tiplication or translation from the VCXO clock frequency. The
VCO PLLs use a high loop bandwidth to assure PLL stability,
so the VCXO must provide a stable low-jitter clock reference
to ensure optimal output jitter performance.
Any unused clock output can be put in Hi-Z mode, which can
be useful for reducing power dissipation as well as reducing
jitter or phase noise on the active clock output.
The TOF pulse can be programmed to indicate the start (top)
of frame and even provide format cross-locking. The output
format registers should be programmed to specify the output
timing format, the output timing offset relative to the reference,
and the initial alignment of reference clock and TOF pulse to
the reference frame. If unused, the TOF output can also be
put in Hi-Z mode.
When a loss of reference occurs during genlock, PLL 1 can
default to either Free run or Holdover operation. When free
run is selected, the output frequency accuracy will be deter-
mined by the external bias on the free run control voltage input
pin, VC_FREERUN. When Holdover is selected, the loop filter
can hold the control voltage to maintain short-term output
phase accuracy for a brief period in order to allow the appli-
cation to select the secondary input reference and re-lock the
outputs. These options in combination with proper PLL 1 loop
response design can provide flexibility to manage output
clock behavior during loss and re-acquisition of the reference.
The reference status and PLL lock status flags can provide
real-time status indication to the application system. The loss
of reference and lock detection thresholds can also be con-
figured.
TABLE 1. LMH1982 PLL and Clock Summary
PLL
PLL 1
PLL 2
PLL 3
PLL 4
Input Reference
H sync
VCXO clock
VCXO clock
VCXO clock
Divider Ratio (reduced)
Programmable
11/4 or 11/2
250/91 or 500/91
5/2
Output Clock
Frequency (MHz)
27
74.25 or 148.5
74.25/1.001 (74.176) or
148.5/1.001 (148.35)
67.5
Output Port
SD_CLK
HD_CLK
HD_CLK
SD_CLK
2.0 GENERAL PROGRAMMING INFORMATION
The LMH1982 can be configured by programming the control
registers via the I²C interface. The I²C_ENABLE pin must be
set low or tied to GND to allow I²C communication; otherwise,
the LMH1982 will not acknowledge communication. The I²C
slave addresses are DCh for write sequences and DDh for
read sequences. See section 8.0 I²C INTERFACE PROTO-
COL and 9.0 I²C INTERFACE CONTROL REGISTER DEF-
INITIONS.
2.1 Recommended Start-Up Programming Sequence
The following programming sequence is necessary to ensure
proper operation of the 148.35 MHz output clock following any
power-up or reset condition. This sequence is also necessary
after changing from any other HD clock frequency or Hi-Z
mode.
1. Program HD_FREQ = 11b and HD_HIZ = 0 (register 08h)
to select and enable the 148.35 MHz HD clock.
2. Program a value of 1 to the following register parameters:
— FB_DIV = 1 (register 04h-05h)
— TOF_RST = 1 (register 09h-0Ah)
— REF_LPFM = 1 (register 0Dh-0Eh)
— EN_TOF_RST = 1 (register 0Ah)
3. Wait at least 1 period of the 27 MHz VCXO clock.
4. Program EN_TOF_RST = 0.
Once this sequence is completed, the 148.35 MHz clock will
operate correctly and normal device configuration can re-
sume. Otherwise, the 148.35 MHz clock may have glitches or
errors until the internal counters of PLL 3 are reset by the
programming sequence above. All other output clocks do not
require this reset sequence for proper operation.
2.2 Enabling Genlock Mode
Upon device power up or reset, the default mode of operation
is Free Run mode. To enable Genlock mode, set GNLK = 1
(register 00h). Refer to section 3.2 Genlock Mode.
2.3 Output Disturbance While Alignment Mode Enabled
While the output alignment mode is enabled (EN_TOF_RST
= 1) and maintained beyond the initial alignment (initializa-
tion), the output signals can be abruptly phase-aligned to the
reference on every output frame. Continual alignment can
cause excessive phase “jumps” or jitter on the output clock
edge coinciding with the TOF pulse; this effect is unavoidable
and can be caused by slight differences in the internal counter
reset timing for the TOF generation and large input jitter. The
characteristic of the output jitter can also vary in severity from
process variation, part variation, and the selected clock ref-
erence frequency. . This output jitter can only be inhibited by
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